Re: [coreboot] SPI Flash does not work on Intel LeafHill CRB

Hi Toan. On BeeProg you can select the offset inside the flash where your image should be loaded to. Just have a look at the lower section in your "load file" dialog box. There is an entry called "Buffer offset for loading". Select positive offset for binary formats and set to 8 MB. That will

Re: [coreboot] Question about Intel HD graphics and FLR

> So long as you don't have to kill anyone to get the info, I genuinely appreciate the help. Question: did you ever kill... Pulling your leg! :-))) ___ Back on the topic/thread: [1] What kind of VM? [2] Does your VM use PCIe Pass-through method (I guess, you must have also in BIOS IOMMU/VT-d

Re: [coreboot] Question about Intel HD graphics and FLR

Joshua, (did you ever watch some James Bond movie with idiom: "if I tell you, then I must kill you?)  > AFAIK, Windows doesn't need a virgin state but the state the VBIOS / GOP > driver usually leaves the hardware in. Plus a Video BIOS Table (VBT) > with some hints about a board's specifics.

Re: [coreboot] Question about Intel HD graphics and FLR

Hi JP, On 30.03.2017 17:48, Joshua Pincus wrote: > Hi Zoran, > > Thanks for your reply. > > My situation is this: When the VM guest comes up the first time from a > system-level reset (aka power on), the Broadwell HD graphics device runs > fine. I see basic VGA both before and during the boot

Re: [coreboot] Question about Intel HD graphics and FLR

Hi Zoran, So long as you don't have to kill anyone to get the info, I genuinely appreciate the help. JP On Thu, Mar 30, 2017 at 9:54 AM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > OK, Joshua! > > I do not promise anything. But I, out of (your) desperation, will try to > find

Re: [coreboot] Question about Intel HD graphics and FLR

OK, Joshua! I do not promise anything. But I, out of (your) desperation, will try to find answers for you. If (no promise)... If I (eventually) return back, I have only one condition for you: NEVER ask how I found (any future) answer for/to you! Thank you, Zoran On Thu, Mar 30, 2017 at 5:48

Re: [coreboot] Question about Intel HD graphics and FLR

Hi Zoran, Thanks for your reply. My situation is this: When the VM guest comes up the first time from a system-level reset (aka power on), the Broadwell HD graphics device runs fine. I see basic VGA both before and during the boot of Windows. Once Windows boots, the HD graphics device is

Re: [coreboot] Lenovo Thinkpad X201: Coreboot incompatible with me_cleaner

On 27/03/2017, Denis 'GNUtoo' Carikli wrote: > On Tue, 21 Mar 2017 14:19:18 + > Sam Kuper wrote: >> Nicola Corna pointed out to me that adding a timeout at >>

Re: [coreboot] Coreboot wiki: what license is the content under?

The wiki is mostly dead, its data mostly useless. Whatever we'll build as its replacement can start with a new, clear license system, and wiki content is either relicensed by its author and then ported over or deleted/rewritten. I'd go with CC-BY for the simple reason that documentation acts as

Re: [coreboot] Coreboot wiki: what license is the content under?

On 28/03/2017, Dumitru Ursu wrote: > On 03/22/2017 12:39 AM, Martin Roth wrote: >> I guess I dislike this as a reason for choosing our license. If some >> future Stack Exchange replacement comes along using a different >> license, what then? We're stuck with what we've already

Re: [coreboot] SPI Flash does not work on Intel LeafHill CRB

On Thu, Mar 30, 2017 at 4:53 AM, Goetz Salzmann wrote: > Dear Toan, > >> I tried as your suggestion: flashed an 8 MB Intel-provided image, read >> back from SPI chip right after flashing, got a 16 MB file (since SPI >> chip is 16 MB size). >> The first 8 MB of 2 files are

Re: [coreboot] Question about Intel HD graphics and FLR

Hello Joshua, I'll ask similar question, considering UEFI (BIOS). I have no idea if you can issue somehow easy FLR (PCI Function Level Reset), but if you can, does this use case repeat itself? I found, related to BIOS, this pointer (

Re: [coreboot] SPI Flash does not work on Intel LeafHill CRB

Dear Goetz, Thanks for your reply. I'm trying to rebuild the image. Another question here: I had an 8 MB Intel-provided image. I'm using BeeProg2C flashing device (with PG4UW software). Is there any "trick" forcing the flashing device to flash 8 MB image into 16 MB SPI chip? Something likes flash

Re: [coreboot] SPI Flash does not work on Intel LeafHill CRB

Dear Toan, > I tried as your suggestion: flashed an 8 MB Intel-provided image, read > back from SPI chip right after flashing, got a 16 MB file (since SPI > chip is 16 MB size). > The first 8 MB of 2 files are exactly the same. So, flashing should > work fine. that's your problem right there.

Re: [coreboot] SPI Flash does not work on Intel LeafHill CRB

Thanks Andrey, that was what I mean. I tried as your suggestion: flashed an 8 MB Intel-provided image, read back from SPI chip right after flashing, got a 16 MB file (since SPI chip is 16 MB size). The first 8 MB of 2 files are exactly the same. So, flashing should work fine. I also went through

[coreboot] [ANN] coreboot community meeting today

Dear coreboot folks, Please don’t miss the coreboot community meeting [1] today. Thanks, Paul [1] https://www.coreboot.org/Coreboot_community_meeting signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Vikings D16: First FSF Respect Your Freedom (RYF) certified mother board

On 2017-03-30 09:28, Paul Menzel wrote: Dear David, Am Donnerstag, den 30.03.2017, 07:40 +0200 schrieb David Hedlund: [[[ To any NSA and FBI agents reading my email: please consider ]]] [[[ whether defending the US Constitution against all enemies, ]]] [[[ foreign or domestic, requires you to

Re: [coreboot] Vikings D16: First FSF Respect Your Freedom (RYF) certified mother board

Dear David, Am Donnerstag, den 30.03.2017, 07:40 +0200 schrieb David Hedlund: > [[[ To any NSA and FBI agents reading my email: please consider ]]] > [[[ whether defending the US Constitution against all enemies, ]]] > [[[ foreign or domestic, requires you to follow Snowden's example. ]]] > [[[

Re: [coreboot] Coreboot 4.5: No early serial output

Fixed. Best I can tell it was due to a clean build as all the other parameters are the same. I had gone back to v4.4 to rebuild and check too, but the problem has persisted. Potentially to do with using .config from a different version of coreboot. But it works so no more investigation ☺.