Re: [coreboot] Will we maintain Skylake/FSP1.1?

You do not know which solution is worse: FSP 1.1, or FSP 2.0?! FSP 1,1 is useless (since many problems in IOTG PED group), and FSP 2.0 is getting more complicated (due to INTEL internal job security protection). It is on your own peril, folks. I should say, at least FSP 2.0 is easier to crack

Re: [coreboot] AMT bug

*A remote hijacking flaw that lurked in Intel chips for seven years was more severe than many people imagined, because it allowed hackers to remotely gain administrative control over huge fleets of computers without entering a password. This is according to technical analyses published Friday.*

[coreboot] ASUS KGPE-D16 Automated Test Failure [master]

The ASUS KGPE-D16 fails verification for branch master as of commit 293445ae1f93d38b86b1c1a3c9ee40ec96a36fac The following tests failed: BOOT_FAILURE Commits since last successful test: 293445a nb/intel/x4x: Add support for second PEG slot See attached log for details This message was

Re: [coreboot] AMT bug

On Tue, May 9, 2017 at 3:25 PM taii...@gmx.com wrote: > > How come risv-v has no DMA security features? ala IOMMU? if you want to > do virtualization that is also a must have due to the performance > differential - you couldn't push 1gbps on a emulated NIC without serious >

Re: [coreboot] Will we maintain Skylake/FSP1.1?

Hi Nico, The Galileo board also supports both FSP 1.1 and FSP 2.0. Lee Leahy (425) 881-4919 Intel Corporation Suite 125 2700 - 156th Ave NE Bellevue, WA 98007-6554 -Original Message- From: Nico Huber [mailto:nic...@gmx.de] Sent: Tuesday, May 9, 2017 3:27 PM To: Youness Alaoui

Re: [coreboot] Will we maintain Skylake/FSP1.1?

On 09.05.2017 18:47, Youness Alaoui wrote: > I thought FSP 1.1 was for skylake and FSP 2.0 for Kabylake, I didn't > realize 2.0 would be compatible with skylake too. Does this mean a skylake > port could use fsp 1.1 or 2.0 ? In that case, is the 2.0 version better > maintained, more stable, easier

Re: [coreboot] Will we maintain Skylake/FSP1.1?

On 09.05.2017 17:19, Aaron Durbin via coreboot wrote: > On Tue, May 9, 2017 at 10:14 AM, Nico Huber wrote: >> Hi, >> >> I was walking through the Skylake FSP1.1 support in coreboot and asked >> myself if it is worth to clean it up and maintain the code? given that >> the

Re: [coreboot] Intel ME The Way of the Static Analysis

ROM Bypass only works on pre-production hardware (e.g. reference boards used for initial development). On production hw it's ignored and mask ROM is always used. Is it possible to buy a reference board if you aren't an OEM? -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] How can improve coreboot and become developer?

the very small group of us doing riscv would certainly be delighted were you to join us :-) On Tue, May 9, 2017 at 12:31 PM serdar tunc wrote: > Hello, > > I am interested in coreboot project. I compiled coreboot, made my own > rom for my x200 and installed via external

Re: [coreboot] kernel payload

On Mon, May 08, 2017 at 06:11:52PM -0400, Healer64 via coreboot wrote: > So the question still remains as to how big the initrd image will be > assuming it has to have the necessities to mount root on lvm encrypted > drive. Any idea? The Heads Linux runtime can mount lvm encrypted drives (along

Re: [coreboot] Recommended memory for coreboot + ASUS KGPE-D16

On 05/08/2017 11:07 AM, Thierry Laurion wrote: Hi, On 04/30/2017 04:46 PM, taii...@gmx.com wrote: On 04/30/2017 08:05 AM, BogDan Vatra wrote: Hi, I'd like to build desktop/workstation for my personal use (lots of compilations + of course gaming on linux) I bought 2 x 6276 CPUs and a

[coreboot] New on blogs.coreboot.org: Announcing coreboot 4.6

A new post titled "Announcing coreboot 4.6" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ We are happy to announce the April 2017 release of coreboot, version 4.6. The 4.6 release covers commit e74f5eaa to commit

Re: [coreboot] ASUS KGPE-D16 IOMMU issue

On 05/04/2017 01:50 PM, low...@airmail.cc wrote: On 2017-05-04 05:52, taii...@gmx.com wrote: Hey silly question did you turn on IOMMU in the vendor BIOS? by default it is off. This is caused by a bad driver or bad hardware, I had a old graphics card that did the same. My D16 works fine and I

Re: [coreboot] Will we maintain Skylake/FSP1.1?

On Tue, May 9, 2017 at 10:14 AM, Nico Huber wrote: > Hi, > > I was walking through the Skylake FSP1.1 support in coreboot and asked > myself if it is worth to clean it up and maintain the code? given that > the upcoming release of Kabylake FSP should be able to supersede

[coreboot] What is the KGPE-D16 PCI audio device for?

I notice the kgpe-d16 has an AMD PCI audio device, but I am curious as to what the purpose of that PCI device is - the weird MIO audio card that ASUS sells appears to have its own realtek chip so I don't think it is that. Is there some kind of header on the board that I am not noticing? does

[coreboot] Will we maintain Skylake/FSP1.1?

Hi, I was walking through the Skylake FSP1.1 support in coreboot and asked myself if it is worth to clean it up and maintain the code? given that the upcoming release of Kabylake FSP should be able to supersede it (I presume it is?). Are there any plans yet to drop it once the next FSP is

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 4 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 4 of 4 defect(s) ** CID 1374934: Memory - illegal accesses (OVERRUN)

Re: [coreboot] Will we maintain Skylake/FSP1.1?

I thought FSP 1.1 was for skylake and FSP 2.0 for Kabylake, I didn't realize 2.0 would be compatible with skylake too. Does this mean a skylake port could use fsp 1.1 or 2.0 ? In that case, is the 2.0 version better maintained, more stable, easier to integrate, etc.. or are both 1.1 and 2.0

Re: [coreboot] kernel payload

I don't know. I thought all initramfs is compressed. Thank you Ron and Duncan for your help. Sent with [ProtonMail](https://protonmail.com) Secure Email. Original Message Subject: Re: [coreboot] kernel payload Local Time: May 8, 2017 4:54 PM UTC Time: May 8, 2017 10:54 PM

Re: [coreboot] kernel payload

is that a compressed or uncompressed initramfs? linux payload can use anything you configure it for. On Mon, May 8, 2017 at 3:22 PM Healer64 wrote: > I guess I will need to do more research about what the minimum > requirements will be. > > Looking at /boot on my

Re: [coreboot] kernel payload

So the question still remains as to how big the initrd image will be assuming it has to have the necessities to mount root on lvm encrypted drive. Any idea? Sent with [ProtonMail](https://protonmail.com) Secure Email. Original Message Subject: Re: [coreboot] kernel payload

Re: [coreboot] kernel payload

no, you have lots of great options with initramfs. So do a file command on your initramfs and see what it is :-) On Mon, May 8, 2017 at 5:28 PM Healer64 wrote: > I don't know. I thought all initramfs is compressed. > > Thank you Ron and Duncan for your help. > > >

Re: [coreboot] kernel payload

I guess I will need to do more research about what the minimum requirements will be. Looking at /boot on my current system the initramfs is about 11Mb, so that would be way too large. Can a linux payload use initramfs or only initrd? Sent with [ProtonMail](https://protonmail.com) Secure Email.

Re: [coreboot] kernel payload

On Mon, May 8, 2017 at 3:11 PM Healer64 wrote: > So the question still remains as to how big the initrd image will be > assuming it has to have the necessities to mount root on lvm encrypted > drive. Any idea? > > > What do you want in there? I'm puzzled that you keep

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

In case you missed it: https://www.tenable.com/blog/rediscovering-the-intel-amt-vulnerability On Fri, May 5, 2017 at 8:10 AM, Peter Stuge wrote: > First, thanks to everyone who is working hard to maintain a good tone > on the list. I certainly appreciate that. > > While the ME

Re: [coreboot] Recommended memory for coreboot + ASUS KGPE-D16

Hi, On 04/30/2017 04:46 PM, taii...@gmx.com wrote: > On 04/30/2017 08:05 AM, BogDan Vatra wrote: > >> Hi, >> >> I'd like to build desktop/workstation for my personal use (lots of >> compilations + of course gaming on linux) >> I bought 2 x 6276 CPUs and a KGPE-D16, eprom programmer, etc. now I'm

[coreboot] How can improve coreboot and become developer?

Hello, I am interested in coreboot project. I compiled coreboot, made my own rom for my x200 and installed via external flasher. And i read a book named "Embedded Firmware Solutions" for understanding coreboots working logic. And im in deadend now. Because i accomplish to have fully operational

[coreboot] AMT bug

There's a good summary about 3/4 way down the page. https://arstechnica.com/security/2017/05/the-hijacking-flaw-that-lurked-in-intel-chips-is-worse-than-anyone-thought/ Just write a simple C/Python/Perl/Go program that sends a 0 length password, done. This certainly seems to show there was no

Re: [coreboot] Intel ME The Way of the Static Analysis

Hello Denis, Tuesday, May 2, 2017, 2:13:13 AM, you wrote: DGC> On Tue, 25 Apr 2017 22:38:15 +0800 DGC> Shawn wrote: >> slide: >> https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf >> >> video: >> https://www.youtube.com/watch?v=2_aokrfcoUk >> DGC> Thanks a