Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
1 new defect(s) introduced to coreboot found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent
build analyzed by Coverity Scan.
New defect(s) R
Hi Juliana, (and anyone else who has opinions)
I'm curious how we should have communicated this better so that we
can improve communication for next year, and for the October
conference in Germany: https://ecc2017.coreboot.org/
Here's what we've done:
1) We've had a banner across the top of the
On Thu, May 25, 2017 at 11:58 AM, Timothy Pearson
wrote:
...
>> It's this a false positive? i.e. it's a problem with the test or
>> actually coreboot doesn't boot?
...
> I've been wondering if I should lower the debug level on the test stand
> for this particular board to mask the problem, or if t
These are the minutes from yesterday's coreboot community meeting.
Information about the next meeting is at the bottom.
The meeting yesterday was very short, with only 5 people attending.
###
Thursday May 25, 2017
General coreb
Hi everybody,
to elaborate a bit on what Martin reported from the community meeting:
In the last few days I set up our server[0] to regularly render our
repositories Documentation/ directory to
https://www.coreboot.org/Documentation/, using hugo for formatting and
conversion.
The old "Documentati
The ASUS KGPE-D16 fails verification for branch master as of commit
6b697ef207674c58b47058b37e11fc97634d5cb4
The following tests failed:
BOOT_FAILURE
Commits since last successful test:
6b697ef util/hugo: no need to enable an interactive terminal
dc5eea1 util/hugo: mark source mounts read-only
7
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/26/2017 10:40 AM, Martin Roth wrote:
> On Thu, May 25, 2017 at 11:58 AM, Timothy Pearson
> wrote:
> ...
>>> It's this a false positive? i.e. it's a problem with the test or
>>> actually coreboot doesn't boot?
> ...
>> I've been wondering if I sh
If one excludes any microcode and the VGA BIOS, is it possible to build a
functioning, blobless coreboot for any Sandy Bridge or Ivy Bridge device
supported? I'm referring here only to the BIOS region on the flash, not the ME
region, IFD and GbE. If the FSP blob is needed, would that be the only
Thomasheidler via coreboot writes:
> If one excludes any microcode and the VGA BIOS, is it possible to build a
> functioning,
> blobless coreboot for any Sandy Bridge or Ivy Bridge device supported? I'm
> referring here
> only to the BIOS region on the flash, not the ME region, IFD and GbE. If
Hi,
On 26.05.2017 21:35, Thomasheidler via coreboot wrote:
> If one excludes any microcode and the VGA BIOS, is it possible to build
if you use the integrated graphics, you don't need a VGA BIOS, there are
replacement options.
> a functioning, blobless coreboot for any Sandy Bridge or Ivy Bridge
Is it possible to find out which Sandy/Ivy board supports native ram/graphics
init before buying one of them? For example, is there some list that shows
compatibility?
Thomas--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
Is it possible to init the graphics device without the radeon bios blob?
such as with openradeonbios or with linux (you could do a petietboot
solution to get graphics pre-OS)
It has no PSP (or obvs ME) and its performance is about equal to a sandy
bridge, so it seems like a great choice if you
On 05/26/2017 04:34 PM, Thomasheidler via coreboot wrote:
Is it possible to find out which Sandy/Ivy board supports native ram/graphics
init before buying one of them? For example, is there some list that shows
compatibility?
Thomas
AFAIK it is only the thinkpad series 2 (ala x220, t420 etc)
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