Re: [coreboot] Some qustion about riscv implement

Thanks for your questions and for looking at the code. It's a new summer and I guess it's time for the riscv privilege model to change again, as it has for the last two summers :-), which means coreboot gets to change too. On Sat, May 27, 2017 at 2:42 AM 王翔 wrote: > # Some

Re: [coreboot] Lenovo G505S blob status?

On 27.05.2017 03:29, taii...@gmx.com wrote: > Is it possible to init the graphics device without the radeon bios blob? > such as with openradeonbios or with linux (you could do a petietboot > solution to get graphics pre-OS) Yes, it's possible and has been done before (e.g. radeonhd and IIRC some

Re: [coreboot] Blobless coreboot on Sandy Bridge and Ivy Bridge?

On 26.05.2017 22:34, Thomasheidler wrote: > Is it possible to find out which Sandy/Ivy board supports native > ram/graphics init before buying one of them? For example, is there some > list that shows compatibility? No list that I know about. But it can be seen from the source (e.g. to support

[coreboot] Some qustion about riscv implement

# Some qustion about riscv implement ## 1. SMP Coreboot for riscv does not support SMP, now. why does the secondary hart not halt in **src/arch/riscv/bootblock.S**? Now, secondary hart halts in **src/arch/riscv/trap_util.S**. This may affect playload implementation. ## 2. Privilege level