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On 03/21/2018 12:47 PM, Daniel Wagner wrote:
> Hi,
Hello Daniel,
thank you for reading 3mdeb blog :)
>
> I would like to test my -rt kernels releases on the minnowboard.
> Though cyclictest always reports 2 to 4 ms spikes. It looks like
> that t
Hello!
I'm working with Haswell+Lynxpoint chip and it has 6 PCIe bridges presented
on one southbridge device "1c" as six functions (I mean "1c.0", "1c.1", ...,
"1c.5"). As I understand, every function (bridge in this example) can drive
only one INTX line of its "1c" device.
For example, function
Hello Daniel,
You need to properly build Coreboot, integrating BYT-I (as I recall
minnow board) FSP, and the info about BYT-I FSP you can find here:
https://github.com/IntelFsp/FSP
Zoran
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On Wed, Mar 21, 2018 at 12:47 PM, Daniel Wagner wrote:
> Hi,
>
> I would like to test my -rt kernels
Hi,
I would like to test my -rt kernels releases on the minnowboard. Though
cyclictest always reports 2 to 4 ms spikes. It looks like that the
original firmware is stealing those cycles. So my plan was to try out
coreboot and see if my theory is correct or not.
Now, I am struggling with getting a
Am 21.03.2018 11:13 schrieb Nico Huber:
On 21.03.2018 00:03, taii...@gmx.com wrote:
On 03/20/2018 06:14 PM, Nico Huber wrote:
These patches need to be added stat
You obviously have no idea what you are talking about.
What makes you say that?
You. You seem to rate the convenience to have a
On 21.03.2018 00:03, taii...@gmx.com wrote:
> On 03/20/2018 06:14 PM, Nico Huber wrote:
>
>>> These patches need to be added stat
>> You obviously have no idea what you are talking about.
> What makes you say that?
You. You seem to rate the convenience to have a binary in the blobs
repository hig
On 21.03.2018 07:00, Paul Menzel wrote:
> Please make sure, that in the coreboot repository `git describe --
> dirty` doesn’t return a string with *dirty* in it. Often it is caused
> by changes in the directory `3rdparty`, which you can fix by running
> `make gitconfig` and `git sup`.
This is futi
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