Privet Ivan,
I would say that Coreboot should go for the greatest and latest. Since
everything from far back in Time is refined, mostly bug free (unless
the new releases do not include some new introduced bugs, which are
fixed (usually) in immediate releases).
This is more matter of the right cho
On 03.04.2018 23:29, Trammell Hudson wrote:
> What ended up working for me was the PC speaker since there is no other
> I/O available so early. I'd really like to thank Uwe Hermann and the
> other devs of libpayload/speaker.c -- I was able to port their driver
> functions to execute very soon afte
On Tue, Apr 3, 2018 at 2:30 PM Trammell Hudson wrote:
>
> What ended up working for me was the PC speaker since there is no other
> I/O available so early. I'd really like to thank Uwe Hermann and the
> other devs of libpayload/speaker.c -- I was able to port their driver
> functions to execute
On Tue, Apr 03, 2018 at 06:32:07PM +0300, Kyösti Mälkki wrote:
> [...]
> > I'm dealing an early bring-up problem on a modern architecture without
> > serial ports and wondering if that would a good way to debug it.
>
> Probably M.2 is not very useful for you... try to look for LPC
> signals, some
I have noticed that both coreboot and seabios are using the very old
versions of LZMA SDK. If we will upgrade our LZMA libraries from the
outdated-by-12-years 4.42 to the current version 18.04 , speed and
compression ratio should improve and maybe a few bugs will be fixed.
Do you think it should be
On Tue, Apr 3, 2018 at 10:26 AM, wrote:
> Folks,
> Can anyone on this list expound on why VbTryLoadKernel() performs a
> sanity-check on bytes_per_lba != 512?
>--->---/*
>--->--- * Sanity-check what we can. FWIW, VbTryLoadKernel() is always
>--->--- * called with only a s
I refer you to the following code:
https://github.com/hephaex/unix-v6/blob/daa355109625a50e6b1080184dee30c9136549d1/param.h#L72
It's this:
/*
* structure to access an
* integer in bytes
*/
struct
{
char lobyte;
char hibyte;
};
What's the point? The point is code linke this:
lpr = (tp->t_speeds
Folks,
Can anyone on this list expound on why VbTryLoadKernel() performs a
sanity-check on bytes_per_lba != 512?
We are working on supporting a board that will require bytes_per_lba ==
4K.
Cheers,
T.mike
--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listin
Hi
On Tue, Apr 3, 2018 at 5:36 PM, Trammell Hudson wrote:
> How soon after reset are port 0x80 messages available on a MiniPCIe
> attached POST card? And would the POST card be expected to work with
> a M.2 to MiniPCIe adapter? How is the ISA bus' I/O address space mapped
> to PCIe devices?
>
On 03.04.2018 03:16, Naresh G. Solanki wrote:
> coreboot-4.7-51-g2ca4ca3f21-dirty Thu Jan 18 22:05:03 UTC 2018
> romstage starting...
> pm1_sts: pm1_en: pm1_cnt:
> gpe0_sts[0]: gpe0_en[0]:
> gpe0_sts[1]: gpe0_en[1]:
> gpe0_sts[2]: gpe0
How soon after reset are port 0x80 messages available on a MiniPCIe
attached POST card? And would the POST card be expected to work with
a M.2 to MiniPCIe adapter? How is the ISA bus' I/O address space mapped
to PCIe devices?
I'm dealing an early bring-up problem on a modern architecture without
Hello everybody!
I have problems with getting coreboot running on a Lenovo ThinkPad
T430.
Better to say: Running with the integrated second graphics adapter NVS
5400M. The Intel HD 4000 is working fine and from the wiki I know that
NVidia Optimus is not supported for now. So what to do exactly
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