Re: [coreboot] Why coreboot for riscv does not support multi-core?

> In short: Because it was easier to delay the problem until later. > >On Thu, May 17, 2018 at 03:55:37PM +0800, 王翔 wrote: >> The current code does not set the stack pointer for hart alone. >> The Linux kernel runs in s-mode and cannot set the stack pointer for m-mode. >> If m-mode does not have a

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 05:21 PM, Banik, Subrata wrote: Hi Subrata, > Can you please check few more things and please help to clarify > some details. > > 1. Is this kind of regression ? because we are not seeing this > issue. Can't tell that it is first

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 02:11 PM, Banik, Subrata wrote: Subrata, > > [Subrata] this specific issue, we haven't seen on any KBL/SKL > system we have. I can double confirm this value tomorrow. For now, > please try to check if increasing timeout is helping

Re: [coreboot] Why coreboot for riscv does not support multi-core?

In short: Because it was easier to delay the problem until later. On Thu, May 17, 2018 at 03:55:37PM +0800, 王翔 wrote: > The current code does not set the stack pointer for hart alone. > The Linux kernel runs in s-mode and cannot set the stack pointer for m-mode. > If m-mode does not have a separat

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 01:51 PM, Banik, Subrata wrote: > Piotr Król, Hi Subrata, > > I have submitted a patch today to overcome some AP timeout issue. > > https://review.coreboot.org/#/c/coreboot/+/26286/ > > Can you please pick this, and see if you ar

[coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi Surbata, I'm trying to enable i7-6500 custom hardware and facing exception when boot flow hit enable_pm_timer_emulation which you submitted in Feb 2017. Stack look like that: Enable ACPI Timer Emulation via MSR 0x121 CPU Index 0 - APIC 0 Unexpect

[coreboot] Why coreboot for riscv does not support multi-core?

The current code does not set the stack pointer for hart alone. The Linux kernel runs in s-mode and cannot set the stack pointer for m-mode. If m-mode does not have a separate stack for hart, then m-mode cannot save any state about the current hart. Is it necessary to initialize the stack pointer

Re: [coreboot] SPI TPM question

Hi! Adding the dependency the code compiles ok, but nothing happens. I've been able to get a TPM2.0 with SPI, a supported SLB9670. I've added select TPM2 select MAINBOARD_HAS_TPM2 select SPI_TPM to the Kconfig of my mainboard/amd/bettong. It compiles ok but nothing happens. I've