Hello Hal,
On 28.05.2018 08:06, Hal Martin wrote:
> Name Offset Type Size Comp
> ...
> cpu_microcode_blob.bin 0x6f00 microcode 0 none
The size looks troubling, I think you really need the correct microcode
binary to get into coreboot
Am Fr., 25. Mai 2018 um 18:40 Uhr schrieb Nico Huber :
> o Set a hard limit around 100 chars (96 would be a nice number).
> o If a line doesn't contain a string literal, recommend a
> visible width <= 72 chars.
As Sam noted, it's hard to find tooling for that.
But even with 96 characters cl
Hi,
Today denverton_core_init() is enabling the Intel SpeedStep only if turbo
mode is available. As a result, the SpeedStep is not enable for the C3558
variant (and others). Any clues of why it was implemented this way?
I think it is safe to remove the "if (get_turbo_state() == TURBO_ENABLED)"
te
Hi,
I suggest you read the wiki :
https://www.coreboot.org/Developer_Manual and
https://www.coreboot.org/Motherboard_Porting_Guide
I would also suggest maybe (optional) that you read my blog posts
about my own experience porting coreboot to a new motherboard :
https://puri.sm/posts/diving-back-int
On 29.05.2018 14:23, Patrick Georgi wrote:
> Am Fr., 25. Mai 2018 um 18:40 Uhr schrieb Nico Huber :
>> o Set a hard limit around 100 chars (96 would be a nice number).
>> o If a line doesn't contain a string literal, recommend a
>> visible width <= 72 chars.
> As Sam noted, it's hard to fin
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Register documentation was published today. Links to the three volumes
(over 7000 pages of documentation!)
https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol1_version1.1_pub.pdf
https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol2_versi
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Sorry, can't add todayit's a little over 6,000 pages of new
documentation. Still, hardly light reading!
On 05/29/2018 03:39 PM, Timothy Pearson wrote:
> Register documentation was published today. Links to the three volumes
> (over 7000 pages
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