Hello,
I am running Coreboor on my X230 which has Windows 10 and Qubes OS
installed.
After some issues I was able to run both OSes encrypted and all devices
(WiFi/WWAN/...) are working under coreboot. (in Qubes and Windows).
Today I found out that I am unable to shutdown or put my laptop to sleep
On 06/21/2018 04:51 AM, Nico Huber wrote:
> On 21.06.2018 03:47, taii...@gmx.com wrote:
>> Ah oops overlooked this.
>> https://review.coreboot.org/#/c/coreboot/+/2531/
>>
>> Paging ron minnich! It seems at the end of the comments various people
>> note the mistake however it never got fixed.
>
> T
Sounds like disabling the PCIe port of the device is the safest solution. Will
switching the value in the devicetree be enough or is that too uncertain?
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i'm going to be talking to them.
On Thu, Jun 21, 2018 at 11:36 AM David Hendricks
wrote:
> I'm calling shenanigans on this. Their server datasheets pretty clearly
> specify an IBV-provided firmware solution, definitely NOT coreboot or
> LinuxBoot and definitely NOT open. I did hear thru the grap
I'm calling shenanigans on this. Their server datasheets pretty clearly
specify an IBV-provided firmware solution, definitely NOT coreboot or
LinuxBoot and definitely NOT open. I did hear thru the grapevine that
they've been in contact with at least one OpenBMC developer, at least.
So basically th
On 21.06.2018 13:20, Jose Trujillo via coreboot wrote:
> If you don't enable a device in devicetree the initialization routine will
> not be executed.
Interpretation of the devicetree on/off values depends on the chipset
code. And even if the chipset code disables (or doesn't enable) some-
thing,
There was an announcement [1] about a new line of servers called
WHITEBOX OPEN (yes, all caps)
which appears to be about servers with Coreboot or Linuxboot and OpenBMC.
Has anyone any experience with this company?
-Alberto
1. https://www.prweb.com/releases/2018/06/prweb15571110.htm
--
coreb
Hello Taiidan and Timothy,
On Thu, Jun 21, 2018 at 01:14:05AM -0500, Timothy Pearson wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
> > https://www.phoronix.com/forums/forum/hardware/motherboards-chipsets/1021175-risc-v-sifive-freedom
If you don't enable a device in devicetree the initialization routine will not
be executed.
To test just insert a SD card and use DMESG or other command to see if device
ID is found, also in device manager in Windows.
JT.
‐‐‐ Original Message ‐‐‐
On June 21, 2018 2:06 PM, Thomasheidle
That's what I'm thinking about, but I am not able to test a build with it
removed from the devicetree to see if that does the trick, so I was wondering
if anybody knows.
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Hello Thomas,
It is not enough just to disable it from the devicetree ?
JT.
‐‐‐ Original Message ‐‐‐
On June 21, 2018 1:43 PM, Thomasheidler via coreboot
wrote:
> Thanks for your response and suggestions.
>
> Luckily I don’t need the SD card reader and would rather completely disabl
Thanks for your response and suggestions.
Luckily I don’t need the SD card reader and would rather completely disable it
to protect against any DMA attack before the kernel initializes IOMMU. The
problem is that I don’t know how to prevent the controller from initializing at
all, short of actua
On 21.06.2018 03:47, taii...@gmx.com wrote:
> Ah oops overlooked this.
> https://review.coreboot.org/#/c/coreboot/+/2531/
>
> Paging ron minnich! It seems at the end of the comments various people
> note the mistake however it never got fixed.
There is no mistake here. The change was only a littl
On 21.06.2018 02:34, Zvi Vered wrote:
> In case of PCIe enumeration, the generation of PCIe (1,2,3) can be set>
> Should vendor supply code for this ? or any other information ?
PCIe configuration is SoC specific and should be done by FSP. However,
I can't find any PCIe specific settings for the
Hello Zvika,
Look for the list of Linux commands to dump many of the information from your
original BIOS running, maybe there you will find this information.
Also, some configuration can be seen from your original BIOS running Intel FIT
for Baytrail in Windows.
About configuring those settings
Hello Zvika,
On 18.06.2018 05:24, Zvi Vered wrote:
> 1. The size of CBFS is: 0x20. Is it a fix size or should I change it
> according to my board (which is also bay trail) ?
on Intel platforms, the SPI flash is shared with other chipset compo-
nents. The CBFS_SIZE should be at most the size o
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