Would be great if someone could help to get libgfxinit working.
On 2018-09-01 21:13, h...@memeware.net wrote:
Cherry picking did not worked for me. I cloned coreboot today on an
new linux installation.
So i did additional:
$ cd 3rdparty/libgfxinit/
$ git checkout master
$ cd -
$ git add 3rdparty
Hello h42,
I am porting a G41M-S3, which is pretty much the same thing but with DDR3
(heck, the component layout is pretty much the same too). I have the same
issue (libgfxinit fails) but I have not done anything about it yet.
Best regards,
Angel Pons
--
coreboot mailing list: coreboot@coreboot
This is my first time using a mailing list btw, sorry.
I was wondering how I could test the images I have built with `make
riscv-crossgcc && make` using qemu.
I tried running qemu-system-riscv64(the one gotten from the riscv-linux
port), with the name of the image produced(coreboot.rom), an
Hi,
We are developing coreboot for Apollo lake custom board.
We would like to reduce the boot time. For this,
* Enabled "MRC training data save" in FSP2_0 using Binary configuration
tool.
But we are receiving the following logs:
NVM Write Failed. Update is lost. If repeatedly encountered,
On Mon, Sep 10, 2018 at 10:03:14AM -0400, Liam Naddell wrote:
> This is my first time using a mailing list btw, sorry.
Hi and welcome,
>
> I was wondering how I could test the images I have built with `make
> riscv-crossgcc && make` using qemu.
>
>
> I tried running qemu-system-riscv64(the one
On Sat, Sep 8, 2018 at 2:31 PM Peter Stuge wrote:
>
> Youness Alaoui wrote:
> > So, back to the ME, we know exactly what it does, it's all extremely
> > well documented and explained
>
> I disagree with this.
>
> It is absolutely true that *some* of what the ME does is extremely well
> documented
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