Hello Zvika:
First get the correct original full 8MB FW from the manufacturer or dump it
from the board with the command in EFI:
"ftp -d BYT_orig.bin" and double save it.
2.- in coreboot/util/ifdtool do make and sudo make install.
3.- in terminal go to the FW directory and do:"ifdtool BYT_or
Hi Ben,
Thanks for your answer! I've been able to trace the 'DxeTpm2MeasureBootHandler'
calls and it's called for each
loaded driver, the GPT table parsing and PeImage loading. Making a full
coreboot and tianocore recompiling has
changed the extended values. The tianocore uses PCRs 1, 4, 5 an
Hello Zvika,
On 9/24/18 9:18 PM, Zvi Vered wrote:
> I have an Intel's ATOM Bay Trail board. The output of "inteltool" is:
>
> CPU: ID 0x30679, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x9
> Northbridge: 8086:0f00 (Bay Trail)
> Southbridge: 8086:0f1c (Bay Trail)
> IGD: 8086:0f31 (unkno
Zvika:
Sorry I Forgot:
"CB_baytrail.bin" is just a renamed copy of "BYT_orig.bin".
After that command a new file will be named: "BYT_orig.bin.new"
Jose.
‐‐‐ Original Message ‐‐‐
On Tuesday, September 25, 2018 10:16 AM, Jose Trujillo
wrote:
> Hello Zvika:
>
> First get the correct origin
Christian Gmeiner wrote:
> Most of the time the system works as expected but from time to rebooting
> the system fails completely.
Only ever when rebooting, or does cold boot also fail sometimes?
(Make a test system to cold boot your system in a loop.)
> there are two FPGAs connected via PCIe t
On Sun, Sep 23, 2018 at 06:42:14PM +0200, Patrick Rudolph wrote:
> Can you make use of the uImage/FIT [1] mechanism coreboot supports ?
> It just needs some architecture specific code.
Good idea. I've seen the FIT support patches and I think FIT looks
reasonable, at least for loading Linux.
Would
On Mon, Sep 24, 2018 at 09:45:40AM -0600, Aaron Durbin via coreboot wrote:
> On Sun, Sep 23, 2018 at 9:00 AM ron minnich wrote:
> >
> > ah sorry I forgot.
> >
> > I think selfboot could be reworked (and should be) to interpret "0" as
> > "somewhere useful"?
Seems like a good idea.
And then the
On 09/24/2018 12:37 AM, Mike Banon wrote:
Hello Anac! I am "mikeb" , wrote these BIOS / KB9012 flashing articles
at DP wiki ;-)
Thanks a lot for that work, your support and sharing all the super
useful info and hints here!
Operating CH341A is very easy: I wrote the instructions for Bus Pir
Am Di., 25. Sep. 2018 um 13:50 Uhr schrieb Jonathan Neuschäfer <
j.neuschae...@gmx.net>:
> Would FIT support require discussion/cooperation with other projects
> like Linux or u-boot?
>
> What seems to be missing is the kernel image format to be used within the
FIT. e.g. look at arm64:
https://git
Thank you for the kind words, Anac ;) another "CH341A advice": check
its' voltage before using for the first time, because there were a few
CH341A (the majority of reports were about black PCB version) , which
- because of manufacturer's mistake - supply 5V power instead of 3.3V
and that could dama
Hi Jose,
Thank you very much for the detail information.
The output of ifdtool in layout.txt is:
:0fff fd
0030:007f bios
1000:002f me
So the original bios size is 0x50 = 5MB
You wrote:
if the size of the original BIOS is bigger or equal than coreboot build
you ar
Hi,
I'm trying to add a way to lock the SPI flash to be read-only via
software *after* coreboot boots. The scenario is basically with using
Heads, you could authenticate to it (with a yubikey/nitrokey/librem
key) then be able to flash a new rom (update your BIOS), but once you
boot an OS, Heads wo
Hi,
I have a quick question. Is there any code in Coreboot to extend the payload to
be loaded in the PCR0 if
the TPM is enabled? I've been able to see the startup command executed but I
don't know if anything else
is implemented. Maybe is this implemented in some staging Coreboot branch?
An
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