Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Peter Stuge
Youness Alaoui wrote: > We don't have/use ChromeEC and I think that telling every user that > they'd need dedicated hardware to update their BIOS makes no sense. I think you can decide what hardware your products include, right? I meant dedicated hardware on the mainboard. > > > Looking for a so

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Sam Kuper
I have been giving Youness's reply some thought. On 29/09/2018, Peter Stuge wrote: > Youness Alaoui wrote: >> On Thu, Sep 27, 2018 at 10:18 PM Sam Kuper wrote: >>> Relevant URL: >>> https://www.chromium.org/chromium-os/ec-development#TOC-Write-Protect >> >> We don't have/use ChromeEC and I think

[coreboot] Fwd: Thinkpad W520 external monitor over Nvdia GPU

2018-09-29 Thread Kinky Nekoboi
Hello ! Thank to charlotteplusplus`s reddit post i have succesfully running coreboot with a skrinked ME image on my W520. Everything works fine exacpt the fact that the nvidia GPU is not reconnicest by any linux distro. (not shown in lspci) is here anyuser with an W520 and got coreboot running wi

Re: [coreboot] Fwd: Thinkpad W520 external monitor over Nvdia GPU

2018-09-29 Thread Iru Cai
The coreboot port of Lenovo W520 is in the upstream code now, are you using the upstream code? On Sat, Sep 29, 2018 at 10:36 PM Kinky Nekoboi wrote: > Hello ! > > Thank to charlotteplusplus`s reddit post i have succesfully running > coreboot with a skrinked ME image on my W520. Everything works

Re: [coreboot] Fwd: Thinkpad W520 external monitor over Nvdia GPU

2018-09-29 Thread kinky_nekoboi
nope, so is the patch for the gpu advertised in the wiki page merged into the upstream code? Am 29. September 2018 16:53:45 MESZ schrieb Iru Cai : >The coreboot port of Lenovo W520 is in the upstream code now, are you >using >the upstream code? > >On Sat, Sep 29, 2018 at 10:36 PM Kinky Nekoboi

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Nico Huber
On 9/27/18 6:24 PM, Lance Zhao wrote: > Okay, then I believe we should leave the decision on CONFIG instead of > force lockdown blindly. As of now, that's still optional I believe. AFAIK, EISS is not a configurable option in coreboot atm. And it shouldn't be, IMHO, as it encourages to weaken secur

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Nico Huber
On 9/28/18 4:18 AM, Sam Kuper wrote: > On 28/09/2018, Peter Stuge wrote: >> Youness Alaoui wrote: >>> avoid any malware writing to the flash >> >> Just disallow flash writes by the platform. Allow flash writes only >> by dedicated hardware (maybe ChromeEC?) which implements a simple and >> efficie

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread ron minnich
It's not a screw in Chromebooks any more, see vadim's excellent OSFC.io talk on how it works now. I think the momentary switch would not be acceptable to anyone for cost and reliability reasons. The way chromebooks do the protection now is really well done. On Sat, Sep 29, 2018 at 8:26 AM Nico Hu

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Nico Huber
On 9/28/18 1:30 AM, Peter Stuge wrote: > Youness Alaoui wrote: >> avoid any malware writing to the flash > > Just disallow flash writes by the platform. Allow flash writes only > by dedicated hardware (maybe ChromeEC?) which implements a simple and > efficient security protocol. It's not as easy

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Nico Huber
On 9/27/18 10:29 PM, Youness Alaoui wrote: > Thanks everyone for the responses. > So far my understanding on the task at hand is : > - Add a CONFIG to decide if we set FLOCKDN or not (and one to decide > if we lock it on the resume path?) Maybe no config at all, see discussion of PRR34_LOCKDN belo

Re: [coreboot] flashrom and 256 MiB S256FL256S

2018-09-29 Thread Nico Huber
On 9/28/18 1:16 AM, Peter Stuge wrote: > ron minnich wrote: >> yeah, also is there a programmer you recommend for 32MiB parts? > > I don't have a recommendation just yet, but a question: > > Speed aside, is single bit IO good enough for 32MiB, or is DIO/QIO required? SIO is generally enough. The

Re: [coreboot] flashrom and 256 MiB S256FL256S

2018-09-29 Thread Nico Huber
On 9/28/18 11:20 PM, ron minnich wrote: > I spoke too soon. It just flat out does not work to have sf100 and 256Mbit > part AFAICT Ah, crap. I just gave this another thought and now I'm convinced that it can't work with the current code. dediprog_spi uses its own functions for read/write that like

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Sam Kuper
On 29/09/2018, ron minnich wrote: > It's not a screw in Chromebooks any more, see vadim's excellent OSFC.io > talk on how it works now. Vadim Bendebury? This talk below? https://osfc.io/talks/google-secure-microcontroller-and-ccd-closed-case-debugging If so, is there a video or audio recording

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread ron minnich
On Sat, Sep 29, 2018 at 1:59 PM Sam Kuper wrote: > Small momentary switches cost pennies and laptops usually have about a > hundred of them fitted, of various kinds. (Power on/off/suspend; > volume up/down; keyboard keys; maybe others.) So, fitting laptops with > momentary switches is definitely

Re: [coreboot] SPI controller and Lock bits

2018-09-29 Thread Sam Kuper
On 29/09/2018, ron minnich wrote: > On Sat, Sep 29, 2018 at 1:59 PM Sam Kuper wrote: >> Small momentary switches cost pennies and laptops usually have about a >> hundred of them fitted, of various kinds. (Power on/off/suspend; >> volume up/down; keyboard keys; maybe others.) So, fitting laptops w

Re: [coreboot] flashrom and 256 MiB S256FL256S

2018-09-29 Thread Nico Huber
On 9/29/18 6:35 PM, Nico Huber wrote: > On 9/28/18 11:20 PM, ron minnich wrote: >> I spoke too soon. It just flat out does not work to have sf100 and 256Mbit >> part AFAICT > > Ah, crap. I just gave this another thought and now I'm convinced that it > can't work with the current code. dediprog_spi