[coreboot] Bootblock CMOS default and the checksum algo

2018-10-06 Thread William McCall
Hey all-- Recently, I started the process of enabling CMOS-based runtime config on a board. As this board is native coreboot and it had never used the CMOS in any meaningful sense, the CMOS was wholly zeroed out. Based on this, the bootblock never programs the defaults. Why? Because the checksum

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread ron minnich
There are people on this list who know better than I what the most "open" one is. Anyone out there have some advice? On Sat, Oct 6, 2018 at 3:17 PM Andrew Luke Nesbit < ullbek...@andrewnesbit.org> wrote: > > On 6 Oct 2018, at 22:17, ron minnich wrote: > > It depends on what you mean by fully. I

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Andrew Luke Nesbit
> On 6 Oct 2018, at 22:17, ron minnich wrote: > > It depends on what you mean by fully. If there is a so-called Mask ROM (i.e. > initial boot program that's part of the chip itself, not replaceable, you can > disassemble it however) and the rest of the chip is fully open, does that > count?

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread ron minnich
It depends on what you mean by fully. If there is a so-called Mask ROM (i.e. initial boot program that's part of the chip itself, not replaceable, you can disassemble it however) and the rest of the chip is fully open, does that count? For my money the ARM chromebooks are still one of the best bet

Re: [coreboot] current state of board/f2a85m

2018-10-06 Thread David Hendricks
There was a status report uploaded about a year ago ( https://coreboot.org/status/board-status.html). Can you verify that the coreboot tree at that commit can boot your system? >From there it will be much easier to find out where things broke. On Sat, Oct 6, 2018 at 5:24 AM kinky_nekoboi wrote:

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Andrew Luke Nesbit
> On 6 Oct 2018, at 17:42, ron minnich wrote: > [...] > > if you really want 100% open, the only real options at this point are power > 9, RISCV and some ARM CPUs. Ron, thanks for your reasoned reply and the contextual background. I believe this is important when embarking on any project

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Zvi Vered
Hi Nico, Thank you very much for the information. Best regards, Zvika On Sat, Oct 6, 2018 at 6:18 PM Nico Huber wrote: > > On 10/6/18 2:46 PM, Zvi Vered wrote: > > Hello Nathaniel, Nico, > > > > Thank you very much for the detailed answers. > > > > The vendor's bin file starts with the following

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread ron minnich
On Fri, Oct 5, 2018 at 9:53 PM Zvi Vered wrote: > > coreboot only replaces the BIOS part developed by vendors like "AMI bios". > > Just to make it clear, it was not always this way. In 1999, 100% of what we call coreboot did 100% of the tasks, and by 2002 it worked on x86, x86_64, powerpc, and a

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Nico Huber
On 10/6/18 2:46 PM, Zvi Vered wrote: > Hello Nathaniel, Nico, > > Thank you very much for the detailed answers. > > The vendor's bin file starts with the following pattern: > : > 0010: 5AA5F00F 03000402 0602100B 20002100 > > Can you confirm th

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Angel Pons
Hello Zvika, The vendor's bin file starts with the following pattern: > : > 0010: 5AA5F00F 03000402 0602100B 20002100 > > Can you confirm that this is the start of IFD ? > The magic "5A A5 F0 0F" at offset 0x10 indicates the start of the IFD.

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Zvi Vered
Hello Nathaniel, Nico, Thank you very much for the detailed answers. The vendor's bin file starts with the following pattern: : 0010: 5AA5F00F 03000402 0602100B 20002100 Can you confirm that this is the start of IFD ? Best regards, Zvika On S

[coreboot] current state of board/f2a85m

2018-10-06 Thread kinky_nekoboi
I was not able to build any usable rom from the current master branch of coreboot for f2a85m. Compliation runs smooth but the resulting system does not pass POST(i dont know how to call it in coreboot terms, the system just powers up and dont loads the SeaBIOS payload) .. no useful debug informat

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Nico Huber
On 10/6/18 6:50 AM, Zvi Vered wrote: > Hello, > > A bin file burned on a BIOS chip contains "Intel FW": > > Intel FW = IFD +PD+ME/TXE+GBE > > IFD=Intel Firmware Descriptor Table. > PD=Parameters > ME=Management Engine (For "Core" kind of processors). > TXE=Trusted Execution Engine (For "Atom" ki

Re: [coreboot] Burn 2MB coreboot.rom on 8MB flash chip

2018-10-06 Thread Nico Huber
Hi Zvi, On 10/5/18 8:46 PM, Zvi Vered wrote: > According to the help of flashrom, it works with bin files only. > So I should take coreboot.rom and stitch it to the parts of the original > vendor's bin file. there is no standard for neither .bin nor .rom files. Most often these file-name extensio

Re: [coreboot] Source code for "Intel Firmware"

2018-10-06 Thread Nathaniel Roach via coreboot
Hi Zvika, In the case of a very limited number of chips, the IFD and GbE regions can be generated, and the ME region skipped entirely (see libreboot/ich9gen). For the others, some reverse engineering may be possible for the IFD and GbE regions but generating even a "me_cleaner" comparable region w

Re: [coreboot] [skylake] Can not turn monitor on

2018-10-06 Thread Nico Huber
Hi Zheng, On 10/6/18 4:58 AM, Zheng Bao wrote: > Sorry for being unclear. no worries, it seems I wasn't very attentive anyway. I just implied you have an integrated (laptop) panel; maybe because you have a mobile processor or maybe because the 1440x900 resolution is common for lap- tops. Anyway,