On 07.06.19 16:24, Alex Feinman wrote:
Indeed this was it. I had a mismatch between the IFD and FMD. As a
result my MRC cache was in the IFD ME region. Obviously the mapper masks
ME region. I think I also have a problem with ME being too large for 16
MB chip (it's 10 MB alone). I might have to
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
34 new defect(s) introduced to coreboot found with Coverity Scan.
17 defect(s), reported by Coverity Scan earlier, were marked fixed in the
recent build analyzed by Coverity Scan.
New defect(s)
Indeed this was it. I had a mismatch between the IFD and FMD. As a result my
MRC cache was in the IFD ME region. Obviously the mapper masks ME region. I
think I also have a problem with ME being too large for 16 MB chip (it's 10 MB
alone). I might have to expand the storage on my board.
Thank
Hi Nico,
That's an interesting idea (IFD). Here is a dump of my IFD, but the problem is
- I am not sure what the regions are and what they should be.
Perhaps I need a region that includes my MRC cache (0x9f)?
File build/coreboot.rom is 16777216 bytes
Found Flash Descriptor signature at
Hi Alex,
On 07.06.19 08:56, Alex Feinman wrote:
I've checked the upper 16 MB - simply dumped the block at 0xff9f
(0xff00 is the last 16 MB + MRC cache region offset 0x9f from
the layout file ) where in my image the MRC cache region resides (I can
confirm it's there by dumping the
I've checked the upper 16 MB - simply dumped the block at 0xff9f
(0xff00 is the last 16 MB + MRC cache region offset 0x9f from the
layout file ) where in my image the MRC cache region resides (I can confirm
it's there by dumping the image from flash). The data I read from the
6 matches
Mail list logo
