Thank you for advice. I followed the instructions of this change, and
after fixing a few compilation errors (had to replace a few %x with
%llu at printf's) - using the same .config - I got a ROM which is
unbootable! Maybe because I don't have AMD HDT Debugger, and it
should've been connected to som
There is unfinished hyperthreading patch for Sandy/Ivy:
https://review.coreboot.org/c/coreboot/+/29669
On 7/2/19 9:33 AM, ashmita.chakrabo...@ltts.com wrote:
> Does the coreboot support the following options to enable/disable:
>
>
> HyperThreading- Disabled
> Execute Disable Bit -
https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/include
I don't believe FSP UPD have everything, they do have P-state I believe.
于2019年7月5日周五 下午1:30写道：
> Hi Lance,
>
> The settings are meant for BroadwellDE not Denverton.
>
> Are these options too supported in BroadwellDE for c
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