@Subrata Banik must have done so on other Intel
project.
In the near future, I think highly possible that CPX FSP will stick with
edk2-stable202005 for quite some time.
Jonathan Zhang (Infra) via coreboot 于2020年6月17日周三
上午3:15写道：
> Hi coreboot colleagues,
>
> Intel EDK2 header files are needed
> Here is what I suggested somewhere on Gerrit [1]:
>
> I was thinking we could move the current `3rdparty/blobs`
> to something like `3rdparty/limited_blobs` or `3rdparty/
> restrictive_blobs`. And guard it like the `amd_blobs`.
> Then move anything without doubts about redistribution
>
Hi coreboot colleagues,
Intel EDK2 header files are needed to build coreboot that depends on FSP. So
far the practice is
to keep such header files under src/vendorcode/intel/edk2 directory, and each
EDK2 version takes
a different directory (we have uefi_2.4, UDK2015, UDK2017).
Since CPX-SP FSP
Hi Sumo,
Thanks for your reply.
As mentioned in my previous mail,.
There are two different fixes which are required for c3558.
a.) The SPEED STEP needs to enabled separately.
b.) APIC id has to be changed under the device tree.
Thanks,
Nitin.
___
Hi,
Looks like for this SoC turbo state is not available, so try the following
(enable speedstep regardless if turbo state is available or not, as you
need speedstep!) :
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -71,11 +71,11 @@ static void
Hello!
Okay Patrick your advice and my decision to upgrade the system worked.
I was able to completely download a new one from the repo.
-
Gregg C Levine gregg.drw...@gmail.com
"This signature fought the Time Wars, time and again."
On Mon, Jun 15, 2020 at 7:31 PM Gregg Levine wrote:
>
>
Sorry for the long silence - I finally found some time to test the HT
patch.
I used coreboot v4.11 as a basis since at this point in time the patch
produced merge conflicts with newer commits.
I used memtest86+ v5.01 (forced SMP, RAM: 16GB @ 1600MHz, CPU: Intel
i7-3840QM) as mentioned in my
Hello!, I wantt to know if the Lenovo R500 has coreboot support without any
blobs
https://phoronix.com/scan.php?page=news_item=Coreboot-4.10-Released
Here it says that is supported
but
https://coreboot.org/status/board-status.html
doesnt appear
and in the tree also no
Another question is if
Hello,
I’m trying to make sense of the information on the Intel website, and the
Coreboot source code, regarding the i3-10110u and i7-10710u processors.
If I have interpreted things correctly, these are Comet Lake U devices and that
the Comet Lake U DDR4 RVP reference board is supported as a
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