Greetings, I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first) It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there? I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me. [1] https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html Sincerely, -Matthew Bradley
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