[coreboot] Re: LPC problem in Coreboot for Apollo Lake

Hello Roman, On 09.09.22 17:48, roman perepelitsin wrote: > I use coreboot for ApolloLake CPU (Atom). We have SuperIO WB83627-DHG chip > on carrier board. LPC enabled, POST codes work normal. But I can't get > access to SIO under Linux (via port 0x2e). Superiotool can't find chip. > Also, I have C

[coreboot] LPC problem in Coreboot for Apollo Lake

I use coreboot for ApolloLake CPU (Atom). We have SuperIO WB83627-DHG chip on carrier board. LPC enabled, POST codes work normal. But I can't get access to SIO under Linux (via port 0x2e). Superiotool can't find chip. Also, I have CPLD on LPCB - I use it to view LPC transactions - so, then I try to

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Re