Re: [coreboot] How to extract fsp.bin from image?

Thank you. It is very useful to me. 2017-01-26 오전 1:45에 Andy Knowles 이(가) 쓴 글: Hi, Use the cbfstool, like so: build/util/cbfstool/cbfstool build/coreboot.rom extract -n fsp.bin -f fsp.bin Good luck! Andy *From:*coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of *???

[coreboot] How to extract fsp.bin from image?

Dear Sir. My Purpose isextract *"Intel fsp.bin"* from bios image. *_First_*, (I was know that get possible "Intel fsp.bin" from Intel website. and already download It is.) This time i have a some bios image. This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI. Another one is

[coreboot] Not running GbE interface.

Dear Sir. My EVB is Rangeley Mohon peak. I was successfuly build and boot the coreboot on my EVB. But, not running the GbE interface. So, I was try to find the mailing list . and Got a some threads. *1. **Message for **G**bE(**This is **perfectly same **that my issue**)*

Re: [coreboot] What purpose the "mrc.cache"?

download it, along with the FSP documentation and the Binary Configuration Tool, from Intel's website: http://intel.com/fsp Martin On Tue, May 31, 2016 at 10:38 PM, 김유석 책임연구원 <kay@hansol.com> wrote: Dear Sir. My ENV. Platform : intel atom rangeley mohon peak CRB(C2358) This tim

[coreboot] What purpose the "mrc.cache"?

Dear Sir. My ENV. Platform : intel atom rangeley mohon peak CRB(C2358) This time, I'm try to study for MRC(Memory Reference Code). But, I'm can not found a some example code on coreboot source tree.(rangely) Anyway, I'm get a some hint on last image. Performing operation on

Re: [coreboot] SeaBios serial(RX) is not running.

Dear Sir. Thank's your work. Enable the bi-direction serial console is done. 2016-05-20 오후 8:36에 Kyösti Mälkki 이(가) 쓴 글: On Tue, May 17, 2016 at 10:46 PM, Martin Roth > wrote: Hi, If you want bi-directional serial port in

[coreboot] How to change the Core input voltage setting?

Dear Sir. My HW enginner required to me. that Change the setting of "Core input voltage". But, I don't know everything this one. Because x86 platform is first time of my develop life. Anyway, I'm try to find the something on coreboot source code. But, still unknow. So, I need a start

[coreboot] How to control the GPIO on x86 rangely?

Dear Sir. My platform is intel rangely. I'm must contol the GPIO pins, But i'm can't found the example code on coreboot source tree. Could you show me the example code to control GPIO? Thank you. -- coreboot mailing list: coreboot@coreboot.org

[coreboot] SeaBios serial(RX) is not running.

Dear Sir. Thank's your advise. everytime. *Finially*, I was succsss the boot using coreboot. But I have a *little problem.* _*I'm can't typing throuth the serial.*_ My x86 BOX is only support serial console. So, Serial console is very important. *But **t**he **Sea**Bios is **Serial