Hi Adrian,
You are better off hooking up to the "Serial Console" port and using that.
http://wiki.minnowboard.org/MinnowBoard_MAX
If you really want to use one of the HS UARTs, then you have a bit of
work to do.
See src/drivers/uart/uart8250mem.c and note the use of
CONFIG_DRIVERS_UART_8250MEM_32
1:57 PM, Martin Roth wrote:
> Do you think we should revert those patches until we can get them fixed?
>
> On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner wrote:
>> FYI -
>>
>> I just tried memtest86 with the popup patches that were added to coreboot.
>> I'm
FYI -
I just tried memtest86 with the popup patches that were added to coreboot.
I'm seeing issues with clearing the background before drawing the SPD popup.
When I hit "c", the "settings" popup shows on both serial and VGA
properly. VGA has a black background and serial clears the area.
When I
It turned out to be a lot easier than I expected.
A patch can be found here:
https://www.coreboot.org/pipermail/seabios/2016-March/010551.html
On Wed, Mar 9, 2016 at 10:40 AM, Ben Gardner wrote:
> Hi All,
>
> Before I get too far investigating adding FMAP support to SeaBIOS, I
> ju
Hi All,
Before I get too far investigating adding FMAP support to SeaBIOS, I
just wanted to check if anyone else is working on this or has done
this.
The goal is to have SeaBIOS look in an alternate CBFS for bootable img/* items.
The plan is to have SeaBIOS find the FMAP location via the
BOOT_ME
I'm all for a sane hosting location of memtest86+.
I marked all patches that I'm current using in my personal tree with
'code-review+2' in gerrit.
I've been sitting on Baytrail support patches.
If you are OK with this being an active branch, I can send those patches along.
Ben
On Mon, Feb 29, 20
Hi Benoit,
There was a bit of a discussion about interrupt routing a while back
(Dec 2015) on FSP Baytrail.
Apparently the IRQs were not swizzled correctly.
https://review.coreboot.org/#/c/12684/
If you are not using a recent version of coreboot, you may need to
back-port that change.
Ben
On W
entioned in the wiki.
That version of coreboot made assumptions about the IFD and ME filename.
The config item was called CONFIG_ME_PATH and it should be the folder
that contains the files "descriptor.bin" and "txe.bin".
Ben
On Tue, Jan 19, 2016 at 1:08 PM, Ben Gardner wrote:
&g
Hi Supriti,
You are supposed to extract the TXE/ME image (and the IFD) from an
existing MbMax BIOS.
Those files may have been customized by the vendor for your board.
Use flashrom to extract the existing BIOS and then use idftool to
extract the sections.
You may also be able to find a MbMax BIOS
e.inc unchanged and get your image right as
> well.
>
> Werner
>
> -Ursprüngliche Nachricht-
> Von: coreboot [mailto:coreboot-boun...@coreboot.org] Im Auftrag von Ben
> Gardner
> Gesendet: Montag, 18. Januar 2016 21:54
> An: Patrick Georgi
> Cc: coreboot
>
Thank you. That worked.
On Mon, Jan 18, 2016 at 2:46 PM, Patrick Georgi wrote:
> 2016-01-18 21:34 GMT+01:00 Ben Gardner :
>> Is there a work-around for this? For example, is there an option to
>> pad the FMAP out to 4 KB?
> The workaround is indeed to increase the FMAP r
Hi all,
With the latest cbfstool in master, the alignment option is broken in cbfstool.
Or rather, the alignment is relative to the CBFS start, not the actual
ROM address, and the 256-byte FMAP throws off the alignment.
In my case, I have a ROM size of 16 MB and the BIOS region starts at 0x20
Hi David,
I've been using eMMC with the baytrail FSP on the E3800 CPU without issue.
I don't recall doing anything special to get it to work under Linux.
Comparing my devicetree.cb with bayleybay_fsp shows these differences
related to eMMC.
I don't know if any of those are important.
register "P
out tomorrow. I know the hardware guy did try to follow all the Intel
> recommendations for the Hooks and such.
>
> We did not make any changes to the GPIO settings the Coreboot defaults to. We
> do that in the custom payload we load.
>
> Brett
>
>
>
>
>
>
Hi Brett,
If you don't mind, I have a few more questions about your setup.
On Thu, Dec 17, 2015 at 10:25 AM, Testerman, Brett (US COM)
wrote:
> I have a custom E38xx design (Baytrail) that I ported Coreboot on to. XDP
> works fine but you must install the TXE image in the boot flash else the
> p
I'm trying to get the XDP debug port working with a custom board that
is very similar to the Minnowmax board.
Has anyone used the XDP connection with the Minnowmax board with coreboot?
Thanks,
Ben
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
>> 3) Make the baytrail directory structures look as similar again -
>> rename the soc/fsp_baytrail/baytrail include directory to
>> soc/fsp_baytrail/soc/include to match what was done with soc/baytrail.
>> Or we can rename them both to just soc/(fsp_)baytrail/include.
>> Something, so long as they
On Mon, Dec 7, 2015 at 9:55 AM, Martin Roth wrote:
> I think we can cut down on some of the code redundancy, but as Alex
> says, they are different chipsets, and we need to be careful about
> trying to combine too much.
>
> Here are my suggested steps:
> 1) Look for commonalities between baytrail
Hi all,
A fix to the timestamp/console issue is available here:
http://review.coreboot.org/#/c/12511/
Would you mind taking a look?
Thanks
Ben
On Sat, Nov 21, 2015 at 10:14 PM, Ben Gardner wrote:
> I think I found the issue, but won't be able to test for another week.
>
> c
grated_base == NULL)
die( "CAR: Could not find migration base!\n");
- offset = (char *)var - (char *)_car_start;
-
return &migrated_base[offset];
}
On Fri, Nov 20, 2015 at 5:11 PM, Ben Gardner wrote:
> On Fri, Nov 20, 2015 at 4:56 PM, Ben Gardner wrot
On Fri, Nov 20, 2015 at 4:56 PM, Ben Gardner wrote:
> Ug. I was looking at the wrong log. Time for a break.
>
> The output from the log was:
> Stack: fef03fc4 or fef03fcc
>
> That seems to match the settings:
> CONFIG_DCACHE_RAM_BASE=0xfef0
> CONFIG_DCACHE_RAM_SIZ
Ug. I was looking at the wrong log. Time for a break.
The output from the log was:
Stack: fef03fc4 or fef03fcc
That seems to match the settings:
CONFIG_DCACHE_RAM_BASE=0xfef0
CONFIG_DCACHE_RAM_SIZE=0x4000
On Fri, Nov 20, 2015 at 4:07 PM, Ben Gardner wrote:
> On Fri, Nov 20, 2015 at 1:23
On Fri, Nov 20, 2015 at 1:23 PM, Ben Gardner wrote:
> On Fri, Nov 20, 2015 at 12:17 PM, Aaron Durbin wrote:
>> On Fri, Nov 20, 2015 at 7:30 AM, Ben Gardner wrote:
>>> Hi Aaron,
>>>
>>> That patch didn't make a difference that I could see. The console
>
On Fri, Nov 20, 2015 at 12:17 PM, Aaron Durbin wrote:
> On Fri, Nov 20, 2015 at 7:30 AM, Ben Gardner wrote:
>> Hi Aaron,
>>
>> That patch didn't make a difference that I could see. The console
>> buffer is still filled with garbage that cbmemc_reinit() copies
The following patch makes my system bootable with the timestamp
corruption issue.
It just stops the log flood.
http://review.coreboot.org/#/c/12506/
I'm still a bit puzzled as to the root cause of the corruption.
Is there additional logging that would be useful?
Thanks,
Ben
--
coreboot mailing
> + }
> +
> /* It's already pointing outside car.global_data. */
> if (*mig_var < _car_start || *mig_var > _car_end)
> return mig_var;
>
> -#if !IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
> - /* Keep console buffer in CAR until
Hi,
I've narrowed down where the CBMEM console is getting corrupted and
found a work around that gets it working again.
It is getting corrupted in the FSP Early Init function. So in the
Intel blob, not coreboot.
I added logs to cbmemc_init() and cbmrmc_reinit() that show the
console pointer, size
if the CBMEM buffers already contain data when they are first
initialized.
How does that memory get cleared?
On Wed, Nov 18, 2015 at 3:24 PM, Ben Gardner wrote:
> More info:
> The console log is also messed up (timestamps are disabled).
> It is looking like something wasn't initia
72 6f 76 69 64 ***..CBFS provid
7adfdff0: 65 72 20 61 63 74 69 76 65 2e 0a 43 42 46 53 20 er active..CBFS
On Wed, Nov 18, 2015 at 2:12 PM, Ben Gardner wrote:
> Hi all,
>
> Has anyone else tried coreboot 4.2 on fsp_baytrail with
> COLLECT_TIMESTAMPS enabled?
>
> I'm se
Hi all,
Has anyone else tried coreboot 4.2 on fsp_baytrail with
COLLECT_TIMESTAMPS enabled?
I'm seeing the console flooded with an infinite loop of "ERROR:
Timestamp table full".
The last few post codes are: 4a 4b 4c 4d.
That puts it in fsp_baytrail / romstage.c in romstage_main_continue():
...
Hi Stefan,
On Mon, Nov 16, 2015 at 2:09 PM, Stefan Reinauer
wrote:
> * Ben Gardner [151116 19:32]:
>> [The previous email got chopped. This is a re-send.]
>>
>> Hi all,
>>
>> I have a 16 MB BIOS flash on a fsp_baytrail based design.
>>
>> I tried ex
Hi Werner,
On Mon, Nov 16, 2015 at 1:04 PM, Werner Zeh wrote:
> Hi Ben.
>
> I currently use a Bay Trail design with 16 MB SPI flash
> of which 14 MB are used for CBFS. I Never have seen such effects on my
> system.
>
> Do you use the latest coreboot tree (master)?
>
> Werner
I'm not on the lates
Hi Patrick,
On Mon, Nov 16, 2015 at 12:54 PM, Patrick Georgi wrote:
> 2015-11-16 19:32 GMT+01:00 Ben Gardner :
>> What is the purpose behind continuing if a bad entry is encountered?
>> It appears that a 'bad' entry only occurs at the end of the CBFS.
> With a properl
[The previous email got chopped. This is a re-send.]
Hi all,
I have a 16 MB BIOS flash on a fsp_baytrail based design.
I tried expanding the CBFS to fill the whole space, but found that to
cause a 10-15 sec boot delay.
The offending code appears to be in cbfs_locate() in lib/cbfs.c:
if (memcmp(
Hi all,
I have a 16 MB BIOS flash on a fsp_baytrail based design.
I tried expanding the CBFS to fill the whole space, but found that to
cause a 10-15 sec boot delay.
The offending code appears to be here:
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/
On Fri, Oct 30, 2015 at 11:52 AM, Aaron Durbin wrote:
> On Fri, Oct 30, 2015 at 9:19 AM, Ben Gardner wrote:
>> cbmem attempts to map 1 MB of memory to read the CB tables.
>> This is failing on my board due to the PAT configuration under Linux.
>> If I boot Linux with "n
cbmem attempts to map 1 MB of memory to read the CB tables.
This is failing on my board due to the PAT configuration under Linux.
If I boot Linux with "nopat", the issue goes away.
I am using the upstream coreboot and SeaBIOS with a custom board based
on the bayleybay_fsp/fsp_baytrail and Linux 4.
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