Re: [coreboot] The GbE is not activated on my Board.

2016-06-29 Thread Berth-Olof Bergman
Hi, The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash. As on

Re: [coreboot] Dead links - missing information?

2015-08-07 Thread Berth-Olof Bergman
I think most of this hardware protection is bullshit. You have remote access to the computer in most operating systems used today. Thus you can login in and operate the computer. You wouldn’t let your neighbor to have a direct connection of keyboard, mouse and screen to your computer, would you

Re: [coreboot] Google Panther: coreboot has to wait for Intel’s ME (Management Engine)

2015-04-28 Thread Berth-Olof Bergman
Anyway, this is very good!! Good work!! > 28 apr 2015 kl. 09:16 skrev Matt DeVillier : > > On 4/28/2015 1:22 AM, Berth-Olof Bergman wrote: >> That’s truly amazing! So the FSP + coreboot part only takes a quarter of a >> second? Intel FSP must be on steroids!! >> &g

Re: [coreboot] Google Panther: coreboot has to wait for Intel’s ME (Management Engine)

2015-04-27 Thread Berth-Olof Bergman
That’s truly amazing! So the FSP + coreboot part only takes a quarter of a second? Intel FSP must be on steroids!! The total boot time is the sum of components time, so if you fix that problem you will have close to a quarter of second boot time!! Can we see a video clip of that boot? > 27 apr

Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201

2015-03-27 Thread Berth-Olof Bergman
Personally I don’t understand why boot loaders insist on writing the code the way they do. There is BIOS services for boot device I/O, serial port debug and putting payloads anywhere in memory. I think a boot loader will suffice running in 16-bit real mode or unreal mode (16-bit code, 32-bit dat

Re: [coreboot] [flashrom] New flashrom logo - fonts

2015-03-13 Thread Berth-Olof Bergman
How about making flashrom available for Bay Trail architecture? > 13 mar 2015 kl. 14:36 skrev Stefan Tauner : > > On Fri, 13 Mar 2015 08:37:49 +0100 > Carl-Daniel Hailfinger wrote: > >> On 11.03.2015 14:30, Stefan Tauner wrote: >>> This will be the last poll that evaluates specific features of

[coreboot] Legacy BIOS

2015-03-09 Thread Berth-Olof Bergman
Hi, Seems you need a legacy BIOS for minnow board max. With legacy BIOS you can run 16, 32 and 64 bit operating systems. We have the fastest booting BIOS for the Bay Trail architecture and it’s pure legacy. Our Bay Trail BIOS will soon be available for Minnow Board Max. Best regards, B-O Berg

[coreboot] Bay trail and SATA legacy IDE mode

2015-02-06 Thread Berth-Olof Bergman
Hi all, Has anyone run a Bay Trail SOC in SATA legacy IDE mode? It doesn’t work on my boards, even though I have identical settings of the PCI configuration space as AMI and Phoenix BIOS. The port works, but the IRQs are wrong polarity. Thus when issuing a command, I don’t get an interrupt. If I