He's trying to advertise his company's legacy BIOS solution.
-Corey
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Oops, sorry, just saw your other mail, and noticed the note in the
wiki to contact the list for details.
-Corey
On Tue, Mar 3, 2015 at 6:16 PM, Corey Osgood wrote:
> http://www.coreboot.org/Board:asus/f2a85-m
>
> On Tue, Mar 3, 2015 at 1:42 PM, David Englund wrote:
>> Is this
http://www.coreboot.org/Board:asus/f2a85-m
On Tue, Mar 3, 2015 at 1:42 PM, David Englund wrote:
> Is this board supported?
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboo
On Mon, Mar 2, 2015 at 9:24 AM, Darmawan Salihun
wrote:
> Hi,
>
> I have checked the list of supported chipset and board but it seems
> that Intel Q45 is not yet in the list. I recall, this chipset is the
> same family with Intel gm45. Anyway, the specific board I'm going to
> port into is Gigabyt
On Mon, Mar 2, 2015 at 12:03 PM, Vadim Bendebury wrote:
> Not that I care much, but I can't help it: this new symbol looks very
> much like the infamous SS Bolts:
> http://www.adl.org/combating-hate/hate-on-display/c/ss-bolts.html#.VPSXeFX3-iw
I can see where you're coming from, but IMO it's a bi
Out of the box, it isn't supported, but the vt82c694 (aka vt694) was
supported in v1, IIRC, and the datasheets and I think even the BIOS
writer's guide are floating around the internet. If you have
experience with C and want to spend some serious time working on it,
it would be a relatively easy bo
On Mar 12, 2014, at 6:56 PM, Kurt QH1 Qiao wrote:
> What about mail server run a script that convert HTML mail to be plain text
> mail?
Most mail clients send html formatted emails as an additional format,
along with the plain text. A script to check for "Content-Type:
multipart/alternative" and
Paul,
Can you please point me to when this became policy on the coreboot
mailing list? I searched, but all I could find was you (and only you)
trying to enforce this netiquette policy, nowhere that it was actually
discussed or adopted.
Also, if you get bored, take the email messages from the last
It's not the time that's the biggest issue here, it's the
documentation. Since around the time of the i945 chipset, Intel has
stopped sharing data crucial to coreboot development, mainly the
location and configuration information on the memory controller
registers, these docs are now only available
Thanks, I'll give it a shot!
Thanks,
Corey
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
I'm working on fixing up the BCom WinNet P680 port, which is a Via C7 CPU
and CN700/VT8237R chipset. I've got it running enough to boot a Memtest86
payload, but it's very slow. The L1 and L2 cache are reported as running at
11-12MB/s by Memtest, which is much slower then they're reported as running
There is no "buy" button on any of their product pages. Email the sales rep
on the right of the screen.
-Corey
On Tue, Jul 2, 2013 at 11:10 AM, Marcello Stanisci
wrote:
> Hi Nico,
> I thought the rk9 is not sold in [1] because there is not a "buy" button.
> Who knows..
> And I actually didn't n
Hi,
I'm currently looking into porting coreboot to the Biostar A68I-350, which
has the E-350 CPU/NB and A68 southbridge. I'm not very familiar with the
AMD end of coreboot or their naming system, but looking at the PCI IDs, it
looks like the A68 is an SB900 (lspci -nn attached). I guess my questio
On Sun, Sep 4, 2011 at 10:58 AM, Lyubomir Minchev wrote:
> Hi All,
>
> I have Laptop HP Pavilion dv4 with Chipset Intel 82801 I (ICH9)
>
> Shall it be compatible with coreboot ?
>
>
The simple answer is no, at this time your chipset is not supported.
-Corey
--
coreboot mailing list: coreboot@co
On Wed, Aug 10, 2011 at 6:51 PM, Stefan Reinauer <
stefan.reina...@coreboot.org> wrote:
> * Dsouza, Malcolm [110809 14:40]:
> > Thanks Corey,
> >
> >
> >
> > 1. I agree that before reading through the code, it is better to first
> check
> > if the BIOS guides are available. However I would s
On Mon, Aug 8, 2011 at 8:33 AM, Dsouza, Malcolm <
malcolm.dso...@igatepatni.com> wrote:
> Hi Everyone,
>
> ** **
>
> I trust all are in the best of health. I am planning to use Coreboot as the
> BIOS for the new Intel 2nd Generation Processors. However Coreboot does
> not support this process
t this point I may just have to wait.
How about a USB flash drive? Is unetbootin an option?
-Corey
>
> On Sun, Jul 10, 2011 at 10:10 PM, Corey Osgood
> wrote:
>>
>> On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote:
>> > Unfortunately, I'm on Windows, so I can&
On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote:
> Unfortunately, I'm on Windows, so I can't really really use the tools listed
> there. If necessary, for instance to rebuild coreboot, I have Debian and
> FreeBSD on a VM, but obviously they can't access information about my
> system. Most of the i
On Thu, Jul 7, 2011 at 6:54 AM, Andreas Galauner wrote:
> On 7/7/11 11:35 AM, Andrew Goodbody wrote:
>> Also I would expect that #4 NC is not NC at all, it just
>> does not go to the SPI device. It could very well be some way to allow
>> safe programming of the onboard SPI device such as by puttin
On Mon, May 16, 2011 at 4:01 PM, Anders jenbo wrote:
> Is there any benefit to actually disabling this stuff?
>
> Mvh Anders
Sometimes it's necessary, like in the case of disabling integrated
graphics to allow a PCI/AGP/PCIe card to work. Other times, like
disabling ps2 and floppy devices, it sha
On Fri, May 13, 2011 at 9:21 PM, Peter Stuge wrote:
> Stefan Reinauer wrote:
2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
>>> This however is a rather advanced platform.
>>>
>>>
>>> coreboot supports none of the components on these platforms.
>>
>> Actually there i
On Tue, May 10, 2011 at 2:10 PM, Vikram Narayanan wrote:
> Hi,
>
> I am using a DELL laptop. The superio used is
> "Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".
>
> Now the thing is there are no serial ports exposed outside in my laptop.
> Is there any other way out to see the d
On Wed, Apr 20, 2011 at 9:07 AM, Philippe LeCavalier
wrote:
> Excerpts from Stefan Reinauer's message of Tue Apr 19 21:30:35 -0400 2011:
>> * Philippe LeCavalier [110419 20:22]:
> [..]
>> If your BIOS works for you, you should consider keeping it.
>>
>> Porting coreboot to a new mainboard is a si
On Mon, Apr 11, 2011 at 8:48 PM, Stefan Reinauer
wrote:
> * Joesph Czerniak [110411 22:22]:
>> Hi,
>> I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It
>> has the following specs:
>>
>> Here are the quick specs (the more detailed specs are at the bottom):
>>
>> CPU: In
On Sun, Apr 10, 2011 at 2:14 AM, ali hagigat wrote:
> I have a general question about a PCI-to-PCI bridge.
> If the device has a positive decoder and receives an address in the
> range of the addresses it should respond. Then it claims the address
> and forwards it to the secondary interface. Now
On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles wrote:
> On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote:
>> Jeremy Moles wrote:
>> > > To clarify, superiotool has functions internally for writing to
>> > > registers in superios,
>> ..
>> > I will need to find whatever register corresponds to G
On Tue, Apr 5, 2011 at 10:38 AM, James Wall wrote:
>
> On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote:
>>
>> 2011/4/5 James Wall :
>> > Hello all,
>> > What is the status of the i865 memory controller?
>>
>> That chipset as a whole is (currently) unsupported, however plans to
>> support it are t
Sorry, your laptop is not supported, and unfortunately probably never
will be. Most laptops have an embedded controller, it's what controls
the screen brightness, lid actions, battery charging, etc, and most
manufacturers of embedded controllers are very reluctant to give out
the datasheets for the
On Sat, Apr 2, 2011 at 8:13 PM, Peter Stuge wrote:
> Hamo wrote:
>> As I want to port Coreboot to ARM, I need to study the structure of
>> Coreboot. Since Coreboot supported PPC once, I want to study the
>> structure of the source code.
>
> Is a good idea.
>
>
>> But I can't find it. Can someone h
now I am assuming we
> should be able to use standard linux
> device drivers to support devices on our board. Is that correct?
>
> Kind Regards,
> Sharib
>
> On Mon, Mar 28, 2011 at 2:31 PM, Corey Osgood
> wrote:
>>
>> Supporting them should be possible, but wo
Supporting them should be possible, but would require documention from
intel that's only available under an RS-NDA.
-Corey
On Mon, Mar 28, 2011 at 4:25 AM, sharib khan wrote:
> Hi,
>
> I am doing a feasibility study to port coreboot on our new generation data
> processing boards.
> We are evalua
I'm from the Bangor, ME area. I don't do coreboot hacking much
anymore, but I might show up if the date and location worked.
-Corey
On Sat, Mar 12, 2011 at 5:07 PM, Anish Patel
wrote:
> how many other new englanders are there on CB?
> maybe portland or boston can do one
>
> On 03/12/11 16:09, Jo
On Thu, Feb 17, 2011 at 11:02 PM, Peter Stuge wrote:
> José Neto wrote:
>> Can you support my motherboard???
>
> No. You will have to do the development yourself, if you want it.
>
>
>> > [Apollo PRO133x] [1106:0691]
>> +-01.0-[:01]00.0 Silicon Integrated Systems [SiS]
>> 300
On Tue, Jan 4, 2011 at 10:43 PM, ali hagigat wrote:
> I am looking for the data sheet and programming reference manual of a
> super I/O chip by ITE, IT8703F.
> I will be much appreciated if anybody can email it for me.
Looks like google can't find it, you're going to have to contact ITE
http://w
On Sun, Jan 2, 2011 at 8:03 PM, Roger wrote:
> I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a
> little mystified on setting the settings.
>
> I can see where settings are set to zero (or default), but when I look at
> other
> settings, the values don't seem to match up
On Thu, Dec 30, 2010 at 5:59 AM, Stefan Reinauer wrote:
> On 12/29/10 4:51 PM, Saku Sammakko wrote:
>
> Hello
>
> Will coreboot work with the following hardware?
>
> Acer Travelmate 8100
> main board (dmidecode): Acer Kingfisher
> cpu: Intel M 730 1,6GHz, 533MHz fsb, 2MB L2 cache
> northbridge (ls
Pass "-fno-stack-protector" to gcc. Second result on a google search
for "__stack_chk_fail", btw.
-Corey
On Thu, Dec 30, 2010 at 2:21 AM, HOAN HOAN LAC LAC wrote:
>
> hi all, can you help me build
>
> Mkelfimage
>
> http://ca9.upanh.com/18.712.23152200.Pfw0/yahoomessenger20101230142043.png
> whe
On Fri, Dec 17, 2010 at 8:19 PM, Patrick Georgi
wrote:
> Hi,
>
> attached to this mail you'll find support for the Intel Poulsbo chipset, the
> first iteration of their System Controller Hub (SCH) designs that integrate
> northbridge and southbridge into a single chip.
>
> Thanks to our work with
On Sat, Oct 16, 2010 at 5:48 PM, Keith Hui wrote:
> But a bit of scheduling headache then awaits. How much CPU init do we
> need to do before we start drawing things in from the cbfs? Is there
> anything that cannot be done until microcode updates are loaded? Is
> cpu_dev_ops.init() an appropriate
On Thu, Oct 14, 2010 at 8:14 PM, Dustin Harrison
wrote:
> Hi,
>
> I tried the instructions for getting serialICE installed, but ran into two
> problems (patch attached solved both problems):
These patches should really go to the serialice mailing list
(serial...@serialice.com). That said, hopefu
On Wed, Oct 13, 2010 at 6:15 PM, Nasa wrote:
>
> - "Peter Stuge" wrote:
>
>> Nasa wrote:
>> > All that said, I was hoping to get pointed in the right direction
>> > to being able to install this in my motherboard. The specifics of
>> > the board (in case I misread the post) are(from manual):
On Thu, Oct 7, 2010 at 5:50 PM, Uwe Hermann wrote:
> See patch.
>
> This works fine (tested in abuild) for all 440BX boards, but it seems to
> break the build of the QEMU target.
>
> I tried to fix it but I don't really know how it can be done. The
> problem is (I guess) that the QEMU target is st
On Mon, Oct 4, 2010 at 6:14 PM, ron minnich wrote:
> On Sun, Oct 3, 2010 at 4:10 PM, Peter Stuge wrote:
>> Rudolf just found a bug in the sb700 code:
>>
>> u32 dword;
>> ..
>> dword = pci_read_config8(dev, 0x64);
>> dword |= 1 << 10;
>> pci_write_config8(dev, 0x64, dword);
>
>
> Actually, I don't
I was thinking of just filtering them by if the email is a member of
the mailing list, and instead of returning an error when the email
isn't a list member (which might pique the spammer's curiousity), just
drop it silently.
-Corey
On Sat, Oct 2, 2010 at 4:18 PM, Gregg Levine wrote:
> On Sat, Oc
On Sat, Oct 2, 2010 at 3:49 AM, ali hagigat wrote:
> Dear Ron Minnich,
> I started with Wiki pages of Coreboot and i found Kontron, 986LCD-mITX
> as a supported mother board. I though its documentation is open
> because Coreboot is open source
Don't blame coreboot for your own misunderstanding. J
On Thu, Sep 16, 2010 at 4:39 PM, Anders Jenbo wrote:
> Just thought it might be fun to implement a totally new chip set :)
> Already have 3 system running Coreboot.
>
> -Anders
Well, if it's Slot 1 it should be SDRAM, so the memory init should be
extremely simple. If you can get the datasheets an
On Thu, Sep 16, 2010 at 1:18 PM, STEMMELIN, FREDERIC (FREDERIC)** CTR
** wrote:
> The computer is booting, and then crashing on Ubuntu logo (10.04 64bits
> version), so far so nice.
In your /etc/default/grub, comment out this line:
GRUB_CMDLIN_LINUX_DEFAULT="quiet splash"
and replace it with
On Sun, Sep 5, 2010 at 2:07 AM, Corey Osgood wrote:
> On Sun, Sep 5, 2010 at 1:46 AM, ali hagigat wrote:
>> Many thanks Corey. The link is OK, i was mistaken.
>> My machine is Linux, Fedora 12, should i execute
>> util/crossgcc/buildgcc to change the GCC of the system?
&g
c/xgcc/bin":$PATH; make
At least I think that's all you've got to do, haven't had to use it yet myself.
-Corey
> If I use Fedora 12 GCC, when it executes 'gcc -Wa,--divide" and the
> option(--divide) is unknown, how come it can compile the files by it
>
On Sun, Sep 5, 2010 at 1:15 AM, ali hagigat wrote:
> Thank you all for the replies.
> Peter, the link you wrote is broken!
> http://sourceware.org/binutils/docs/as/i386_002dOptions.html#i386_002dOptions
Works fine for me:
--divide
On SVR4-derived platforms, the character `/' is treated as a
On Mon, Aug 30, 2010 at 9:52 PM, Warren Turkal wrote:
> I clearly included the patch without my sign off. Here's another
> exported from my git tree.
Acked-by: Corey Osgood
And committed in r5761.
Is RCBA/ACPI support in the works?
-Corey
--
coreboot mailing list: coreboot@c
On Tue, Aug 31, 2010 at 10:25 PM, illdred wrote:
> On Wed, 1 Sep 2010 02:51:10 +0200
> Peter Stuge wrote:
>
>> illdred wrote:
>> > I would like to use coreboot on my machine.
>> ..
>> > VIA C7 cpu, VIA CN896 northbirdge, VIA 8237A southbridge
>> ..
>> > Will it work?
>>
>> No, not without develop
2010/8/25 Stefan Reinauer :
> See patch
>
> --
Acked-by: Corey Osgood
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Please disregard, cbfstool should be 64-bit on 64-bit platforms, the
error I was getting was just a glitch.
On Mon, Aug 23, 2010 at 12:55 AM, Corey Osgood wrote:
> Add -m32 to the cbfstool LDFLAGS, to fix compilation on 64-bit distros
> (Ubuntu 10.04 here).
>
> Signed-off-by:
Add -m32 to the cbfstool LDFLAGS, to fix compilation on 64-bit distros
(Ubuntu 10.04 here).
Signed-off-by: Corey Osgood
Index: util/cbfstool/Makefile
===
--- util/cbfstool/Makefile (revision 5737)
+++ util/cbfstool/Makefile (working
On Wed, Aug 18, 2010 at 4:24 PM, xdrudis wrote:
> On Wed, Aug 18, 2010 at 03:07:04PM -0400, Corey Osgood wrote:
>>
>> Most of the code in these files is trivial and identical to every
>> other super IO, with the exception of changing the model name/number.
>> If we kept
On Wed, Aug 18, 2010 at 11:25 AM, Peter Stuge wrote:
> repository service wrote:
>> Log:
>> Support for Fintek F71863FG.
>
> It looks to me like this code is identical to the previous fintek
> code which it was copied from. Why can the old code not be re-used,
> instead of creating a copy?
>
> And
On Thu, Aug 5, 2010 at 3:38 PM, Myles Watson wrote:
> On Thu, Aug 5, 2010 at 1:18 PM, Joe Korty wrote:
>> On Thu, Aug 05, 2010 at 01:40:35PM -0400, Myles Watson wrote:
>>> I like using a pushpin best:
>>> http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools
>>>
>>> A bios savior can
On Wed, Aug 4, 2010 at 5:21 AM, Paul Menzel
wrote:
> Dear Corey,
>
>
> Am Donnerstag, den 29.07.2010, 20:22 -0400 schrieb Corey Osgood:
>> Add support for the Intel NM10 (a variant of ICH7) and ICH8
>> southbridges.
>> Both are tested and appear to be working, howev
your help, I wouldn't have known where to begin
> without it.
>
> Quoting Corey Osgood :
>> Please try the attached patch, and run memtest for a while (overnight
>> would probably be best), and let me/us know the results. If this seems
>> to correct the issue, then I&
On Wed, Aug 4, 2010 at 5:13 AM, Paul Menzel
wrote:
> Am Mittwoch, den 04.08.2010, 03:36 -0400 schrieb Corey Osgood:
>> Patch attached, and output below (from Zotac NM10 board)
>
> It looks like you picked the wrong file in the file chooser. `Makefile`
> is attached.
>
Oops
Ping?
On Thu, Jul 29, 2010 at 8:22 PM, Corey Osgood wrote:
> Patch attached.
>
> -Corey
>
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Patch attached, and output below (from Zotac NM10 board)
superiotool r5679
Found Winbond Nuvoton NCT5571D (id=0xb3, rev=0x53) at 0x2e
Register dump:
idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val ff b3 53 ff 00 40 00 00 ff 20 00 00 7f 0a 00 00 83
def RR b3 NA ff 00 40 00 MM ff 20
On Mon, Aug 2, 2010 at 10:52 PM, Corey Osgood wrote:
> On Mon, Aug 2, 2010 at 3:44 PM, ron minnich wrote:
>> On Mon, Aug 2, 2010 at 2:53 PM, wrote:
>>
>>> I'm not sure what other info might be useful, but I'll provide it or try
>>> whatever is aske
Please try the attached patch, and run memtest for a while (overnight
would probably be best), and let me/us know the results. If this seems
to correct the issue, then I'll work on a patch to initialize the
extra ranks.
Thanks,
Corey
On Tue, Aug 3, 2010 at 5:38 PM, Corey Osgood wrote:
&
Yeah, I'm wondering if it's maybe that there's 2 ranks and each one
needs to be initialized seperately, but only one is getting
initialized. IT took away internet access on my linux box at work, so
I can write a patch to test it out, but I can't send it until I get
home (in about 7 hours)
-Corey
On Mon, Aug 2, 2010 at 3:44 PM, ron minnich wrote:
> On Mon, Aug 2, 2010 at 2:53 PM, wrote:
>
>> I'm not sure what other info might be useful, but I'll provide it or try
>> whatever is asked. A few other possible clues: the factory bios only
>> recognized half of my installed ram, but coreboot
> you can run up to memtest indicates that there _is_ RAM. :-)
>
> For testing you could try to disable HAVE_HIGH_TABLES - if memtest works
> then, your memtest doesn't know the forwarder entry we introduced last
> year or so.
>
>
> Patrick
>
> --
> coreboot
Acked-by: Corey Osgood
2010/7/31 Björn Busse :
>
>
>
> This message was sent using IMP, the Internet Messaging Program.
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.or
On Fri, Jul 30, 2010 at 2:20 PM, wrote:
> Quoting Patrick Georgi :
>
>> Am 30.07.2010 19:35, schrieb austi...@msu.edu:
>>>
>>> I have a Jetway 7F4K1G5S-LF board I'm trying to get working.
>>
>> Just to make things clear - that's a Via C7 board, yes?
>
> Yes.
>
>>> Any ideas?
>>
>> We moved the C7
Patch attached.
-Corey
Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood
Index: g
On Thu, Jul 29, 2010 at 11:10 AM, ron minnich wrote:
> Is there a good ref. board to buy to try it out?
The Zotan NM-10 DTX board has 2 PCI-E ports (one x16 one x1), a
mini-PCI-E, 2 DDR2 slots, a serial header, and socketed SPI flash,
which is why I chose it. Oh, and everyone on the Zotac forums
Committed, r5673, with a couple minor changes (remove an unnecessary
read, add full stops).
Thanks,
Corey
On Thu, Jul 29, 2010 at 3:12 PM, Stefan Reinauer
wrote:
> On 7/29/10 8:10 PM, ron minnich wrote:
>> Is there a good ref. board to buy to try it out?
>>
>> ron
>>
> The Intel Seed Board Prog
functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood
Index: inteltool.h
===
--- inteltool.h (revision 5670)
+++ inteltool.h (working copy)
@@ -62,6 +63,7 @@
#define
The package I bought (from Newegg) has the built-in NM-10 video
onboard, and also includes a PCI-E 1x ION graphics card. I will try to
get both working.
On Wed, Jul 21, 2010 at 4:38 AM, Corey Osgood wrote:
> This is my current project, Intel Atom D410/510 cpu and NM10
> southbridge support
very day.
>
>
> On Wed, Jul 21, 2010 at 5:53 PM, Corey Osgood
> wrote:
>>
>> I think I just need to clarify a couple things:
>>
>> On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood
>> wrote:
>> > On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat
>>
I think I just need to clarify a couple things:
On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood wrote:
> On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat wrote:
>> My first impression from the BIOS open source project was an effort to
>> expand knowledge not to earn money!!
There are
On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat wrote:
> My first impression from the BIOS open source project was an effort to
> expand knowledge not to earn money!!
>
> If any one wants to earn money he will find a technical job, will get
> involved in deadlines of the project, will tolerate the pr
This is my current project, Intel Atom D410/510 cpu and NM10
southbridge support. There's 2 different IONs, one is a full chipset,
the other is just a graphics chip. Supporting the graphics chip/card
isn't very difficult, just load the vendor bios, it's the chipset that
we can't do without any docs
On Sun, Jul 18, 2010 at 12:30 PM, Michael Karcher
wrote:
> Am Sonntag, den 18.07.2010, 18:20 +0200 schrieb Carl-Daniel Hailfinger:
>> > There is no ISP header, and the flash chip is socketed,
>> > the board will be a Zotac Atom/NM10 ITX board.
>> You could stack two SPI chips easily, and switch th
On Sun, Jul 18, 2010 at 1:11 PM, Rudolf Marek wrote:
> Hi,
>
> I guess you need to have some driver to disconnect the bus from chipset.
> And maybe some diode not to power on whole MB while doing ISP when MB is off
> Check this:
>
> www.dediprog.com/chipset/via8237s.pdf
>
> Maybe you will need tri
The file that you're looking for is src/pc80/isa-dma.c. I suspect that
isa dma init isn't actually shutting the system down, just resetting
whatever COM you're getting serial output from. Either comment out
that dma port, or try re-initializing the serial console after doing
isa_dma_init().
-Corey
Please check the coreboot wiki, most of those utilities should have
entries or are mentioned there. Some of them also have README files
inside, which explain their purpose. If neither of those applies, then
most likely it's either an obsolete tool, or something that was
written for one specific boa
I need a way that I can test images without actually being in the same
location as the board I'll be testing them on. What would you guys
recommend for programming an SPI chip with it still on the
motherboard? There is no ISP header, and the flash chip is socketed,
the board will be a Zotac Atom/NM
It's been a while since I've read the list, and I've got a new project
going on and I'm trying to get back up to speed. I see there's now a
v4, currently checking it out but it looks a lot like the v2 code with
the v3 build system, is that about right? If so, sorry I wasn't around
to help out with
Sorry, my cn700 system died, and I've been too busy with other
projects to replace it. I haven't been following the list for a while,
so I don't know what the current state of vga bios loaders can do, and
when I do get back to working on my carpc, I'll most likely be working
on an intel board, than
Richard,
There are several boards currently running without SPD data, the one I'm
looking at right now is the pcengines alix1c. Have a look at how it works
there, it seems like a reasonable way to do things.
-Corey
On Thu, May 28, 2009 at 4:07 AM, Richard Smith wrote:
> Peter Stuge wrote:
>
>>
You've got an intel 965 chipset, which isn't supported by coreboot. Laptops
also present a challenge for coreboot, and at the moment there are none
supported. Sorry, but support for your laptop probably won't be happening in
the near future.
-Corey
On Wed, May 20, 2009 at 3:38 AM, blah blah wrote
I don't have time to fix right now, but see Config.lb in the
src/mainboard/** directory for the mew-vm. You're looking for the
ide0_enable flag, it needs to be added to the same file for the mew-am.
-Corey
On Fri, May 15, 2009 at 3:29 PM, Lim, Vincent wrote:
> Hi All:
>
> There is a build erro
On Tue, May 12, 2009 at 6:16 AM, Joseph Smith wrote:
>
>
>
> On Mon, 11 May 2009 20:54:38 +0200, Quentin RAMEAU
> wrote:
> > Hi,
> >
> > I have got a Veriton FP2 (
> > http://www.acersupport.com/desktop/html/vfp2.html)
> > with a S511P motherboard, Intel 82815 northbridge and 82801BA
> southbrid
On Sun, May 10, 2009 at 6:34 PM, Elia Yehuda wrote:
> here is the comment from my previous patch, revealing most of my RE work :
>
>
> /* TODO: This needs to be calculated according to the DRAM tech
> * (x8, x16, or x32). Argh, Intel provides no docs on this!
> * Currently, it needs
TABLES being disabled since it disables (for unknown reason)
> the onboard VGA.
>
> Signed-off-by: Elia Yehuda
>
Acked-by: Corey Osgood
Where did you find the info on configuring the BUFF_SC registers? Also, the
lack of high tables breaks something (SeaBIOS or CBFS?) but I have
Can someone test serial console on COM2 with the new libpayload-based FILO?
With the old FILO it's working fine, but with the new one I get nothing, and
I don't have a COM1 to test on.
Thanks,
Corey
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Mon, Apr 27, 2009 at 3:26 PM, ron minnich wrote:
> I think moving the v3 style printk to v2 makes the most sense.
If we're going to keep spending time making v2 more v3-like (printk, CBFS,
Kconfig, etc), then why even bother with v3? v3 seems like it's got some
really great advantages, but n
2009/4/24 Raphaël Maville
> Hi!
>
> Well so I sent lspci yet! What then ? Please ?
>
Your chipset is supported by flashrom, which means that the flash chip is
probably hidden behind an embedded controller. Without datasheets and/or
physical hardware access, it's almost impossible to support you
On Fri, Apr 24, 2009 at 12:03 PM, Gregg Levine wrote:
> On Fri, Apr 24, 2009 at 11:38 AM, Joseph Smith
> wrote:
> >
> >
> >
> > On Fri, 24 Apr 2009 11:31:58 -0400, Ward Vandewege wrote:
> >> On Fri, Apr 24, 2009 at 11:26:55AM +0200, Rudolf Marek wrote:
> >>> Can someone test if
> >>>
> >>
> >
>
On Wed, Apr 22, 2009 at 2:32 PM, Joseph Smith wrote:
>
>
>
> On Mon, 20 Apr 2009 11:27:38 -0400, Joseph Smith
> wrote:
> > Hello,
> > I keep getting unexpected exception errors on my IP1000 with builds over
> > the past 6 months or so. The unexpected exception errors are random
> errors
> > and
On Mon, Apr 20, 2009 at 10:18 AM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2...@gmx.net> wrote:
> On 20.04.2009 15:43, Luc Verhaegen wrote:
> > On Mon, Apr 20, 2009 at 03:16:13PM +0200, Carl-Daniel Hailfinger wrote:
> >
> >> Should I now revert the table part of the patch because I nak it and
On Sun, Apr 19, 2009 at 8:41 PM, wrote:
> Hello
>
> Anyone can tell me how to make the difference between the 1605A and the
> 1605D ?
> From the datasheet, the "D" accept some more opcodes. Great, but, how to
> differenciate both ?
> I check the datasheets, but... see no differences in RDID or R
2009/4/16 Raphaël Maville
> Well had not time to open the laptop;
>
> I have tried something: else: phnxdeco (phoenix bios decoder) on the
> update "bios.wph" from the vendor site (HP):
>
> Sorry, I am speaky below, because I do not know what is usefull!
>
>
> phnxdeco seem to be only to read bio
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