Its OK, I'm flexible. Do whatever everyone decides is right, I just need to
move on to other things.
Thanks,
Dan Lykowski
From: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
To: Li, Maggie maggie...@amd.com
Cc: Marc Jones marcj...@gmail.com; Dan
Sorry for the delay.. Way too much to do and so little time..
Fixed the spotted issues and added 1ms delay to match the BKDG while waiting
for BAR+0xe to set its bits.
Dan Lykowski
Signed-off-by: Dan Lykowskilyko...@gmail.com
From: Li, Maggie maggie
[0.524338] PREFETCH window: 0xfdb0-0xfdbf
There are some pretty big differences. If we can explain them away great! if
not, it would seem we have an allocation problem somewhere.
Thanks,
Dan Lykowski
From: Stefan Reinauer ste
. Is this incorrect
also? What would be the best way to get the SMBus? Is the device being stored
somewhere that I don't currently see?
Thanks,
Dan Lykowski
--- On Sun, 2/1/09, Li, Maggie maggie...@amd.com wrote:
From: Li, Maggie maggie...@amd.com
Subject: Re: [coreboot] SB600 HDA can't find codec fix
. There were unneeded things happening.
So here is the second try.
Thanks,
Dan Lykowski
Signed-off-by: Dan Lykowski lyko...@gmail.com
Index: src/southbridge/amd/sb600/sb600_hda.c
===
--- src/southbridge/amd/sb600/sb600_hda.c
Can anyone point me in the right direction as to where the Bridge Mem
Window/Prefetch Window PCI configurations are defined/setup/used/etc. Coreboot
does not set these correctly in my case. ( As compared to the standard BIOS )
Thanks,
Dan Lykowski
--
coreboot mailing list: coreboot
These changes allow the SB600 HDA to detect the codec correctly. I haven't had
time to test the sound output, but Linux now detects it correctly. I don't see
why it wouldn't work. Feel free to give it a whirl and let me know if more work
is needed.
Signed-off-by: Dan Lykowskilyko...@gmail.com
, I was just trying
to keeps things minimal.
Thanks,
Dan Lykowski
--- On Sat, 1/24/09, Peter Stuge pe...@stuge.se wrote:
From: Peter Stuge pe...@stuge.se
Subject: Re: [coreboot] [PATCH] Remove reset in SB600 SATA speed fall down
To: coreboot@coreboot.org
Date: Saturday, January 24, 2009, 7:00 PM
similar as expected. By telling the kernel to use the
advanced IO_APIC, I can finally boot to a prompt.
Next issue to resolve... X11 with fglrx...
Is this the right list to post FILO patches?
I've attached my PIRQ and MPtables for your reading enjoyment.
Dan Lykowski
/* generated
seems to assign incorrect interrupts at random. Is it possible to dump an
ACPI table and reuse it?
I am able to boot all 3 ways with the original BIOS.
I have attached the mptable.c and irq_tables.c from the SOM-5781 690/600 board
I have been working on.
Thanks
Dan Lykowski
incorrect interrupts at random. Is it possible to dump
an ACPI table and reuse it?
I am able to boot all 3 ways with the original BIOS.
I have attached the mptable.c and irq_tables.c from the SOM-5781 690/600
board I have been working on.
Thanks
Dan Lykowski
/* This file was generated by getpir.c
Grub2 does:
device_reg = 0xE0 | (slave)?slave_bits:master_bits
I believe this would be correct for FILO:
cmd.device = IDE_DH_DEFAULT | IDE_DH_HEAD(0) | IDE_DH_LBA | info-slave
This of course is just a hunch at the moment. I won't be able to try it until
Monday.
Thanks,
Dan Lykowski
SATA is Bus 0: Dev 18: Func 0 in the docs.
How/Why/Where did it get 0:12:0 ? in the OS and in some places in CB(dts)?
Am I mixing two different things up? I would like to know what I am missing.
Thanks,
Dan Lykowski
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org
Subject: Re: [coreboot] FILO and SATA on 690/600
To: Dan Lykowski engineerguy3...@yahoo.com
Cc: Coreboot coreboot@coreboot.org
Date: Friday, January 16, 2009, 3:01 PM
-Inline Attachment Follows-
I have another question dealing with PCI numbering if someone has the time
to answer
command line.
Thanks,
Dan Lykowski
--- On Sat, 1/17/09, Peter Stuge pe...@stuge.se wrote:
From: Peter Stuge pe...@stuge.se
Subject: Re: [coreboot] FILO and SATA on 690/600
To: coreboot@coreboot.org
Date: Saturday, January 17, 2009, 1:09 AM
-Inline Attachment Follows-
Dan Lykowski wrote:
Has
.
This patch includes the changes I submitted a few days ago that haven't been
acked yet.
I now have a working Coreboot system. ( Although SATA needs a little work so I
am not booting linux yet. ) But at least FILO comes up.
Dan Lykowski
Signed-off-by: Dan Lykowski lyko...@gmail.com
So now I will remember to attach the patch.
Dan Lykowski
Signed-off-by: Dan Lykowski lyko...@gmail.com
--- On Wed, 1/14/09, Dan Lykowski engineerguy3...@yahoo.com wrote:
From: Dan Lykowski engineerguy3...@yahoo.com
Subject: [coreboot] [PATCH] fixes ram init when processor doesn't have FID
Adds a retry/faildown to SB600 SATA detection logic.
SATA port status kept returning 0x1: BAR5+po+28h
1h = Device presence detected but Phy communication not established
This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g.
Thanks
Dan Lykowski
Signed-off-by: Dan
Second attempt with the spaces fixed.
Signed-off-by: Dan Lykowski lyko...@gmail.com
Dan Lykowski
--- On Thu, 1/8/09, Bao, Zheng zheng@amd.com wrote:
From: Bao, Zheng zheng@amd.com
Subject: Re: [coreboot] [patch] Proposed patch for FIDVID question
To: Dan Lykowski engineerguy3
be read from MSR(0xC0010015).
Thanks,
Dan Lykowski
Signed-off-by: Dan Lykowski lyko...@gmail.com
---
Index: src/northbridge/amd/amdk8/raminit_f.c
===
--- src/northbridge/amd/amdk8/raminit_f.c (revision 3855)
+++ src
I would suggest this part:
http://www.innodisk.com/flashstorage_specification.jsp?flashid=29
They plug right in to the SATA port.
They have a minor quirk where you have to 'force.libata=1:1.5g' to get them to
work under Linux but that is the only negative I have run across so far.
Dan Lykowski
The manufacturer makes them in a number of form factors.
In the form I have on hand, it plugs right in to a standard motherboard SATA
slot without a cable. I have to connect an external +5V supply from the power
supply.
Dan Lykowski
--- On Mon, 1/12/09, Tom Sylla tsy...@gmail.com wrote:
From
333Mhz
333Mhz
Thanks,
Dan Lykowski
Signed-off-by: Dan Lykowski lyko...@gmail.com
--- On Thu, 1/8/09, Marc Jones marcj...@gmail.com wrote:
From: Marc Jones marcj...@gmail.com
Subject: Re
cpuid_result cpuid1;
cpuid1 = cpuid(0x807);
if( (cpuid1.edx 0x06) == 0x06 ) {
}
S1G1 Sempron 2100+ 9W 1Ghz
Thanks,
Dan Lykowski
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Patch to add support for Winbond w83627uhg SuperIO.
(This is my first submission. Let me know if I did it wrong.)
Signed-off-by: Dan Lykowski lyko...@gmail.com
---
Index: src/superio/winbond/w83627uhg/w83627uhg_early_serial.c
this?
Thanks
Dan Lykowski
--- On Wed, 12/31/08, ron minnich rminn...@gmail.com wrote:
From: ron minnich rminn...@gmail.com
Subject: Re: [coreboot] 690/600 Just starting out.
To: Bao, Zheng zheng@amd.com
Cc: engineerguy3...@yahoo.com, coreboot@coreboot.org
Date: Wednesday, December 31, 2008
seen this before? It keeps happening over and over. I'll be looking
in to it tonight. My understanding so far is that it is only supposed to happen
once.
Thanks
Dan Lykowski
coreboot-2.0.0 Tue Dec 30 10:32:31 PST 2008 starting...
bsp_apicid=0x0
core0 started:
SBLink=00
NC node|link=00
27 matches
Mail list logo
