/me starts searching for working FSP.
With the current (BayTrailFspGold004_3) FSP from github and the
microcode from the 3rdparty dir
(3rdparty/soc/intel/baytrail/microcode_blob.h) I get it finally booting
a Linux system.
Thanks for all the tips.
Daniel
--
coreboot mailing list: coreboot@c
Hi Piotr,
This will give you layout file similar to: :0fff fd
0040:007f bios 1000:003f me :0fff
gbe
I got this as well. Zoran just told me offline that fd and gbe
seems to overlap. He also told me that the layout should be fd,
gbe, me and finally bios. Is
Hi Michael and Zoran,
On 03/22/2018 08:45 PM, Zoran Stojsavljevic wrote:
IIRC, there are two types of BYT-i used for IOTG, in INTEL. The CPUIDs
are 0x30673 (for Revision B) and 0x30679 (for Revision D). You can
retrieve CPUID using simplistic CLI: dmesg | grep microcode after
bringing Linux up:
Hi Piotr,
On 03/21/2018 09:49 PM, Piotr Król wrote:
> thank you for reading 3mdeb blog :)
Thanks for taking time to write your findings up. Very useful.
> MinnowBoard is already integrated. What board are you using ? Is this
> MinnowBoard Turbot B ?
It is the Turbot but I don't remember if it i
Hi,
I would like to test my -rt kernels releases on the minnowboard. Though
cyclictest always reports 2 to 4 ms spikes. It looks like that the
original firmware is stealing those cycles. So my plan was to try out
coreboot and see if my theory is correct or not.
Now, I am struggling with getting a
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