Re: [coreboot] Off-topic: what's a fast, easily accessible I/O (pin)?

Hi Stefan, On Wed, Dec 5, 2012 at 6:55 PM, Stefan Tauner wrote: > Hi, > > if you would want to measure the instant in time you do something() in > software with a scope or logic analyser (by toggling a pin once) on a > typical x86 PC (e.g. pci, serial, lpt available, ok maybe not THAT > typical a

Re: [coreboot] Asus F2A85-M progress

Hi all, On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban wrote: > > On Mon, Dec 17, 2012 at 2:33 PM, wrote: > > Rudolf Marek writes: > >> Maybe it is slowly time to prepare a patch, I think I will need to write a > >> porting guide + specific AGESA bits. > > > > I would be really helpful if you

Re: [coreboot] Asus F2A85-M progress

Hi Idwer, On Tue, Dec 18, 2012 at 4:41 AM, Idwer Vollering wrote: >> I got SerialICE to start up and respond to simple commands. (I haven't >> run the BIOS image in Qemu yet, but commands such as *mb work.) >> >> I selected the Asus M4A77TD_PRO board. Since SerialICE only needs to >> know how to

Re: [coreboot] new to list

Hi Stuart, On Sat, Dec 29, 2012 at 6:21 AM, Stuart Stevenson wrote: > Gentlemen, > I am new to this list. > I am looking for a fast boot setup for Linux. > My search leads me to think/hope coreboot has the flexibility to support a > very fast boot time eg 1 to 3 seconds. > > I would like more in

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

Hi Rex, On Mon, Dec 31, 2012 at 12:08 PM, Andrew Goodbody wrote: > On 30/12/12 17:26, Rex Djere wrote: > >> I did a lot of research for the article, and I feel that I got a >> pretty good picture regarding what happened with AMD, coreboot, and >> UEFI/secure boot. I am looking for 2 things pleas

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On Wed, Jan 2, 2013 at 11:04 AM, ron minnich wrote: > On Wed, Jan 2, 2013 at 9:58 AM, Andrew Goodbody > wrote: > > > I am sure that it is the old story, most testing will be done against > > Windows. Anything more will be the exception. This is where the pressure > > needs to be put on the platf

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On Thu, Jan 3, 2013 at 4:23 PM, gary sheppard wrote: > I very much wish people would listen to what Ron just said! > > As for why they are lining up behind it? Personally I think they are > afraid to be seen as "reactionary" and against "progress". After all > "everyone" knows secureboot will mak

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

Hi Andrew, On Fri, Jan 4, 2013 at 5:09 PM, Andrew Goodbody wrote: > > Enrol your own key. Sign your own kernel. Seems to scale linearly per user > to me. > > Security is not free. There will always be a cost. > > I am actually quite conflicted because I try to look out for the underdog in every f

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

Hi Andrew, On Fri, Jan 4, 2013 at 4:23 PM, Andrew Goodbody wrote: > On 02/01/13 19:28, David Hubbard wrote: > >> Andrew, Ron, what's your take on >> http://mjg59.dreamwidth.org/**20916.html<http://mjg59.dreamwidth.org/20916.html>? >> >> Specifically:

Re: [coreboot] Permanent solution of the UEFI Secure Boot problem?!

Hi Svetoslav, On Wed, Jan 9, 2013 at 2:48 PM, Svetoslav Trochev < svetoslav.troc...@gmail.com> wrote: > Hi Everyone and Happy New Year. > > This summer I'm planning to buy new laptop. > Also ongoing debates related to UEFI transition and current implementation > of 'Secure Boot' requirement impo

Re: [coreboot] building a coreboot (and 100% free software) compatible box

Hi Csillag, On Wed, Feb 6, 2013 at 6:58 PM, "Kristóf, Csillag" < csillag.kris...@gmail.com> wrote: > Hi, > > I am looking to build a new computer very soon, and I would like to ask > for your advice about it, especially about software supports. > > My requirements are the following: > > 1. Absolu

Re: [coreboot] coreboot 2013 Google Summer of Code: Call for mentors and project ideas

On Sat, Mar 16, 2013 at 2:00 PM, smithb...@gmail.com wrote: > On 03/15/2013 01:10 PM, Marc Jones wrote: > > ever before. coreboot on shipping devices from AMD, Google, and >> > > As I haven't been very active lately what's shipping from AMD these days. > I know whats from Google. Are there prod

Re: [coreboot] f2a85-m related topics

On Tue, Mar 26, 2013 at 1:11 PM, Rudolf Marek wrote: > Hi all > > The board is finally in. I'm aware that David bought it (i think he has > f2a85-m CSM version which is USA specific), is there anyone else? > PaulePanter maybe? > > Has anyone tried "hot flashing" ? It seems linux crashes if I simp

Re: [coreboot] f2a85-m related topics

On Wed, Mar 27, 2013 at 9:32 AM, Martin Roth wrote: > On 03/26/2013 01:11 PM, Rudolf Marek wrote: > >> Hi all >> >> The board is finally in. I'm aware that David bought it (i think he has >> f2a85-m CSM version which is USA specific), is there anyone else? >> PaulePanter maybe? >> >> Has anyone t

Re: [coreboot] ASRock E350M1: How to set RAM voltages under coreboot?

On Sun, Apr 21, 2013 at 5:43 AM, Rudolf Marek wrote: > In the long term, would it be possible to do this stuff from the OS, >> not some bios setup screen? Or is it too late by the time the OS is >> booted? On the SiS 630 we controlled overclocking parameters via a >> user mode command once Linux

Re: [coreboot] UDELAY_IO

If Rudolf isn't opposed, I'd like to try submitting the fix to move the f2a85-m/Kconfig select UDELAY_LAPIC to the CPU instead. David -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] UDELAY_IO

http://review.coreboot.org/#/c/3178/ Tested the change on F2A85-M with no issues. David -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] DDR fails on F2A85-M

Hi Rudolf, Paul, I pulled the version from http://review.coreboot.org/#/c/3200/ but my F2A85-M still halts in the same place: ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c', line 263 I am using CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_150 I uncommented the #d

Re: [coreboot] DDR fails on F2A85-M

> > If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back > > to DDR3-667 or try an intermediate speed, say DDR3-1333 ? > > Maybe there is an option in AGESA where you can limit the maximum > frequency. > > $ more src/mainboard/asus/f2a85-m/buildOpts.c > […] > #define BLDCFG_MEM

Re: [coreboot] DDR fails on F2A85-M

The board does boot, but only at DDR667. (I tried each option up to DDR1600) On Tue, May 21, 2013 at 7:19 PM, David Hubbard < david.c.hubbard+coreb...@gmail.com> wrote: > > > If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go > back > > > to DDR3

Re: [coreboot] DDR fails on F2A85-M

On Wed, May 22, 2013 at 9:49 AM, Ward Vandewege wrote: > > On Wed, May 22, 2013 at 11:18:46AM -0400, Ward Vandewege wrote: > > However, hd/strings suggest that the AGESA version is v1.1.0.7: > > > > 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 > > |AGESA...| > > 206210

[coreboot] Native init for AMD cards

Hi all, I read the kernel sources today, looking for a way of doing native init for AMD boards like the F2A85-M. My CPU has a Radeon HD 7660D built in; lspci says 00:01.0 VGA ... Trinity [Radeon HD 7660D] drivers/gpu/drm/radeon/radeon_asic.c - int radeon_asic_init() handles Trinity like this:

Re: [coreboot] Native init for AMD cards

On Mon, May 27, 2013 at 11:46 PM, ron minnich wrote: > > On Mon, May 27, 2013 at 9:45 PM, David Hubbard > wrote: > > > 1. How hard would it be to import the kernel code into coreboot directly? > > > > don't. You should do a lot of extraction using coccinell

Re: [coreboot] gratis bricked x60s

Hi Tim, I would hope there is a way you could get your x60s working again. Perhaps the next time there is a coreboot get together you could bring it, and arrange for someone to bring a flashrom programmer. Yes, I am mildly interested in saving the x60s from the rubbish heap. But I live in the US.

Re: [coreboot] Fixed the bug of rs780 gfx port A

Hi, Do a search for "RS780" on http://www.coreboot.org/Supported_Motherboards You'll find these motherboards: ASUS M4A785-M: contact Juhe ASUS M4A785T-M: contact GNUtoo ASUS M4A78LT-M: contact Idl0r ASUS M4A78-EM: contact Juhe Jetway A78VM5: I couldn't find a contact AMD Tilapia and Mahogany: I

Re: [coreboot] Native init for AMD cards

Hi Ron, Rudolf, I've attached a shell script that does the first part of preparing the in-kernel radeon driver for coreboot. I settled on a shell script after thinking about what coccinelle is best used for. It does look like coccinelle could do what ctags does, namely, find function definitions.

Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)

Hi Sebastian, On Thu, Jul 4, 2013 at 3:14 PM, Sebastian Parborg wrote: > I've made some more progress in this matter. I got rid of more coreboot > log errors and warning messages. I also managed to get rid off most of the > warnings the linux kernel prints when it boots. > However it seems like

Re: [coreboot] How to add prints to the boot screen

Hi Pankaj, Please provide lots of details, such as: what board are you using? What is your coreboot config? Coreboot itself will not print things on the VGA console. You should look at the payload if you want to customize the boot screen. David On Wed, Jul 10, 2013 at 12:50 PM, Pankaj Chhabra

Re: [coreboot] Supported laptops (again), treacherous computing

On Fri, Jul 12, 2013 at 9:42 AM, ron minnich wrote: > It's kind of useless to point to a bunch of random laptops with a > compatible chipset. It's never that simple. You don't know what the EC > is or how to talk to it, and you don't have critical info you need to > really make this work. So coun

[coreboot] Asus F2A85-M: is seabios patch still needed?

Hi Rudolf, I just tried booting coreboot with vgabios.bin as per http://www.coreboot.org/ASUS_F2A85-M but *without* the seabios patch there. The system boots ok, the on-CPU graphics are initialized, and everything seems to be working. I am using seabios head (ed88f6515c18d9520efa4a41ccb70038dfbe4

Re: [coreboot] Well supported energy efficient HTPC motherboard

Hi Oliver, Ouch, those are pretty big numbers. I was acking towards the Asus F2A85 > aswell but will probably look at a very power efficient APU variant. Don't > they come in 65W TDP's? Granted these tdp's are including a GPU. > Keep in mind I'm measuring at the wall. TDP is the rating just for t

Re: [coreboot] Well supported energy efficient HTPC motherboard

A more efficient PSU might save a few watts. Just a thought. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Tyan s2912-e (fam10h)

Hi Mark, On Sat, Sep 7, 2013 at 9:38 AM, Mark Mc wrote: > Hi, I was hoping someone could help me out or point me in the right > direction with a tyan s2912-e board not booting with coreboot, > 2x 2419 opterons > 16GB ECC DDR2 RAM > Onbard SAS LSI 1064e > AMD Radeon 7850 2GB > > the codes on the

Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs

On Mon, Sep 9, 2013 at 10:17 PM, Peter Stuge wrote: > Andrew Wu wrote: > > You can see util/crossgcc/Makefile : > > > > > > all: build > > > > build: > > bash ./buildgcc -G -p i386-elf > > bash ./buildgcc -G -p armv7a-eabi > > IMNSHO this is a stupid problem seriously in need of an intell

Re: [coreboot] Implementing or not implementing hacks for the OS (was: Change in coreboot[master]: ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1)

Hi all, On Sun, Oct 13, 2013 at 2:03 PM, ron minnich wrote: > Paul, you missed part of the picture. Suppose we have a different > kernel, which does not have the same bug as Linux has,and that, > further, depends on that register being visible? We can't know that > such OSes exist, but we do not

Re: [coreboot] BadBIOS Thoughts

On Sun, Nov 3, 2013 at 4:50 PM, Gregg Levine wrote: > "Trust but verify." > "Trust but verify" became famous in the US after President Ronald Reagan's use of it during the Nuclear Disarmament treaty negotiations. It is originally a Russian proverb, "doveryai, no proveryai" I wonder what Mr. Rea

Re: [coreboot] looking for a good, small, low power, portable board

Hi Ron, Is stackability or rack-mount also a plus? Any particular power requirements or limits? I assume you've already looked at standard sizes like mini-ITX; can you clarify what rules that out? Regards, David -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/li

Re: [coreboot] looking for a good, small, low power, portable board

The Asus F2A85-M has the same NIC (RTL8111, uses the r8169 kernel module). It has only one bug I'm aware of: https://bugzilla.kernel.org/show_bug.cgi?id=55841 On Tue, Nov 26, 2013 at 1:36 PM, Bruce Griffith wrote: > On Mon, Nov 25, 2013 at 3:28 AM, ron minnich

Re: [coreboot] Hack A Day is slamming the PCduino

On Tue, Dec 10, 2013 at 3:41 PM, Gregg Levine wrote: > Hello! > It is interesting. A number of weeks after Ron brought up the > existence of this gadget, the site I track the availability of > discussed the thing. > > Basically they are trying to stay out of the argument, but the > comments are qu

Re: [coreboot] coreboot on amd A85 can't work

I am also very familiar with that particular message. I had a failing CPU and I ended up replacing parts until it booted ok. Like Idwer said: it is not able to initialize any DDR3 RAM. There is a #define that will turn on verbose output about the DDR3 link training if the Vendor BIOS (from Asus) t

Re: [coreboot] Overclocking AMD Trinity processors

The AGESA source sets up the PLLs for the various function blocks on the chip. I just want to try to warn you not to overclock your CPU. Or, use the vendor BIOS to do it. Overclocking relies on knowing the motherboard layout, timing, and thermal characteristics to a degree of detail that just isn'

Re: [coreboot] coreboot on amd A85 can't work

-- Original -- > *From: * "David Hubbard"; > *Date: * Tue, Dec 17, 2013 05:56 AM > *To: * "Idwer Vollering"; > *Cc: * "coreboot"; "陈军根"; > *Subject: * Re: [coreboot] coreboot on amd A85 can't work > > I

Re: [coreboot] coreboot on amd A85 can't work

Ok, the log looks like the one I got when my machine was unable to find the RAM. I suggest a different CPU. I realize that's a hard thing to do, and it's ok to use the exact same type of CPU (A10-5800K). It fixed the problem for my F2A85 and A10-5800K. The only other option I can think of is to n

Re: [coreboot] coreboot on amd A85 can't work

-- Original ------ > *From: * "David Hubbard"; > *Date: * Sat, Dec 21, 2013 02:46 PM > *To: * "陈军根"; "Coreboot"; > *Subject: * Re: [coreboot] coreboot on amd A85 can't work > > Ok, the log looks like the one I got when my machine was unable to

Re: [coreboot] Binary situation

Hi Rudolf, On Mon, Dec 23, 2013 at 3:21 PM, Rudolf Marek wrote: > Hi all > > https://www.coreboot.org/Binary_situation > > Some time ago Patrick started a https://www.coreboot.org/Binary_situationpage > which I updated in the past days. It monitors the various blobs and > firmwares in the Intel

Re: [coreboot] Are any Chromebooks able to run fully libre?

On Sat, Jan 4, 2014 at 4:14 AM, Sam Kuper wrote: > What would you recommend as a good primer (textbook; website; manual; > whatever) that would give someone with limited experience enough knowledge > to avoid making that mistake and others like it? > > I think Peter means the IBM PC architecture:

Re: [coreboot] coreboot engineer needed

Hi Scott, Without additional information about the following questions, the job offer misses some candidates. Still, in this economy, kudos for the offer. 1. What does "coreboot engineer" mean? An engineer who has experience with coreboot -- or an engineer who will be working openly, supporting t

Re: [coreboot] Pavilion Chromebook 14 (Butterfly) Q&A session

On Mon, Jan 20, 2014 at 11:48 AM, mrnuke wrote: > On Monday, January 20, 2014 12:37:30 PM you wrote: > > I have some questions about this little guy. Fear not, your answers will > be > > ported to the coreboot wiki at my earliest convenience. > > > > 1. What is the maximum amount of RAM that it s

Re: [coreboot] Researching the SMM mode

On Wed, Feb 5, 2014 at 8:08 AM, Ramkumar Ramachandra wrote: > Hi, > > I'm currently researching the SMM mode, and would appreciate pointers > on what the code in src/cpu/x86/smm does. > > 1. It seems to me that smi_handler() is executed everytime there's an > SMI interrupt. When does this occur? H

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On Thu, Feb 6, 2014 at 12:28 AM, HacKurx wrote: > > OK. Please can you enable AGESA debug stuff. It should produce more > > output. > > > > You can do that by uncommenting #define IDSOPT_IDS_ENABLED in mainboard > > directory OptionsIds.h file. > > > > We dont have a menuconfig for that yet. > >

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On Mon, Feb 10, 2014 at 11:59 AM, David Hubbard < david.c.hubbard+coreb...@gmail.com> wrote: > On Mon, Feb 10, 2014 at 12:16 AM, HacKurx wrote: > >> > Please double check IDSOPT_IDS_ENABLED. >> > >> > I have first-hand experience with Rudolf's sugge

Re: [coreboot] Asus f2a85-m binary blobs?

I think your answer is pretty well answered here: http://www.coreboot.org/Binary_situation The section "recent AMD" covers the f2a85-m binary situation. David On Fri, Feb 14, 2014 at 8:09 AM, Dominic Walden wrote: > Hello, > > I apologise if this has been asked before, but is it possible to ru

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On Tue, Feb 25, 2014 at 1:39 PM, HacKurx wrote: > > Scott wrote: > > > > The cupid is not found because trinity support is included but > > richland support is needed. I do not know if forcing the trinity > > code to run on richland will work, but you could try it. One way > > to try it is to cha

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On Wed, Feb 26, 2014 at 12:54 PM, HacKurx wrote: > > David wrote: > > With just 1 stick in the A1 slot, please post a pastebin of the console > > output. > > Perfect! It is perfectly detailed, the cpu is not recognized: > http://pastebin.com/2Lbew82b > > Great, this is another big step in the rig

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On Thu, Feb 27, 2014 at 2:53 PM, HacKurx wrote: > > David wrote: > > It would still be helpful if you can post the details for this stick. > 1 Corsair CMV4GX3M1A1333C9 (4Gb & 1,5 Volt) > http://www.ldlc.com/fiche/PB00104214.html > > > You may also want to post the output of "git diff" for others

Re: [coreboot] qemu

On Sunday, March 09, 2014 08:26:05 PM you wrote: > On Sunday, March 09, 2014 05:14:51 PM you wrote: > > Story so far: > > > > 1. pick q35 chipset > > 2. qemu -M q35 etc. etc. > > $ qemu-system-i386 -M q35 --bios build/coreboot.rom > > -ENOREPRODUCE > > > 1. pick i440fx chipset. > > 2. qemu -M pc et

Re: [coreboot] I've turned on paging as a test

On Wednesday, March 12, 2014 08:03:04 AM ron minnich wrote: > > On Wed, Mar 12, 2014 at 6:33 AM, Peter Stuge wrote: > > > Do we want ACPI? > > > > We've had it for years. Do we want UEFI runtime services? They're > required > > for ARM V8 ;-( > > > Are you telling me something like linux will hav

Re: [coreboot] Changes to the coreboot Project Structure

On Thu, Mar 20, 2014 at 9:31 PM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> wrote: > On 21.03.2014 01:39, Carl-Daniel Hailfinger wrote: > > Hi Stefan, > > > > streamlining development and maintenance is definitely absoutely > > worthwhile. Getting rid of unmaintained code is also a

Re: [coreboot] [announce] coreboot for the 21st century

On Fri, Mar 21, 2014 at 4:28 PM, ron minnich wrote: > On Fri, Mar 21, 2014 at 1:33 PM, mrnuke wrote: > > On Saturday, March 22, 2014 03:56:46 AM Andrew Wu wrote: > >> Yes, that is right. DMP/Vortex86EX has no MTRR. So it maybe a problem > >> if without romcc. :( > > > > Is there any way whatsoev

Re: [coreboot] Changes to the coreboot Project Structure

On Sat, Mar 22, 2014 at 9:10 PM, Peter Stuge wrote: > Vladimir 'φ-coder/phcoder' Serbinenko wrote: > > The proposition of gatekeepers would essentially kill community effort. > > That might not be a bad thing. > > Unfortunately, considering how the hardware industry works, individual > contributo

Re: [coreboot] Changes to the coreboot Project Structure

On Sun, Mar 23, 2014 at 12:58 PM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> wrote: > On 23.03.2014 19:24, ron minnich wrote: > > So I believe the problem is not the idea of gatekeepers, but the > > manner in which they are proposed to work. Can you tell me what about > > this upse

Re: [coreboot] New addendums to INTEL FSP family

On Wed, Apr 2, 2014 at 11:08 AM, ron minnich wrote: > On Wed, Apr 2, 2014 at 9:38 AM, mrnuke wrote: > > That is a clear attempt to circumvent the > > wishes of the rightsholders to this project. > > > > > That part I believe you are missing here is that this is a balancing > act. The vendors ar

Re: [coreboot] Life hack #37: how to make a great touchpad

On Sun, Apr 20, 2014 at 9:45 PM, mrnuke wrote: > To manufacturers of Chromebooks, > > Sorry guys, I have a chromebook myself, and its touchpad is appalling. I've > also tried the chromebooks in stores and they aren't much better. > > But have no fear, Alex is here, and has the perfect recipe on h

Re: [coreboot] USB tick in SMM?

On Tue, Apr 29, 2014 at 11:36 AM, ron minnich wrote: > Anybody out there know typical numbers for the timer tick if USB is > active as part of SMM? > > I just heard one number for one product line, 8 HZ. We're seeing a > mysterious 18 HZ tick on one system. Any other numbers people know? > 18.2

Re: [coreboot] f2a85m and e350m1 dmidecode

ng list archive. I can't remember off the top of my head, though. > On 18/08/14 04:43, David Hubbard wrote: > > For f2a85 BIOS rev 5103 (an older version): > > > > # dmidecode 2.11 SMBIOS 2.7 present. 66 structures occupying 2602 > > bytes. Table at 0x000EB330. &

Re: [coreboot] IBM x60t test - DSDT is in fact incomplete

On Sun, Aug 24, 2014 at 8:39 PM, Charles Devereaux wrote: > > Hello > > Previously ( http://www.coreboot.org/pipermail/coreboot/2014-July/078320.html) I mentioned that 3 bugs seemed to be related to the DSDT: > - missing ACPI events when the stylus is inserted/removed > - errors when trying to m

Re: [coreboot] IBM x60t test - DSDT is in fact incomplete

Hi Charles, I'm focusing in on this error message first: ACPI Warning: For \_SB_.PCI0.LPCB.EC__.LED_: Excess arguments - needs 1, found 2 Can you take a look at the .asl files in your coreboot build? I believe you will find something like "Method (LED, 2, NotSerialized)" which means the LED meth

Re: [coreboot] New board with unsupported cpu, chipset, and superIO

On Thu, Aug 28, 2014 at 11:28 AM, Todd Weaver wrote: > >> It appears "If it is not supported by coreboot then you will have a lot > >> of work in front of you." > > > > This view, is based on not having the Intel code and writing your own code > > to set up the DRAM controllers. I imagine that it

Re: [coreboot] F2A85-M + A10-5800K hangs

Hi Torsten, On Tue, Sep 30, 2014 at 6:26 AM, Torsten Duwe wrote: > > Hi all, > > I've gotten myself an f2a85-m and a known-good trinity CPU > A10-5800K (AD580KWOHJBOX), flashed a recent coreboot and... > it hangs. At least I'm getting some debug: > > > | coreboot-4.0-6970-g81f90c5 Sun Sep 28 23:1

Re: [coreboot] Suggested readings

On Mon, Oct 6, 2014 at 8:28 AM, Aaron Durbin wrote: > On Mon, Oct 6, 2014 at 9:42 AM, wrote: > > Dear cb folks, > > > > I ask you some advice on material that is worth reading in order to gain > > fundamental notions on computer architecture. > > > > Which book do you suggest to that purpose? >

Re: [coreboot] AMD's binary-only AGESA libraries

> What do you think … ? I am happy Kyösti has written such a good analysis of the situation. Thank you! I only have one question and one business-level observation. First, the observation: AMD can't abandon the open-source AGESA. It *does* affect business decisions to go with AMD over Intel: Inte

Re: [coreboot] AMD's binary-only AGESA libraries

On Thu, Nov 6, 2014 at 8:32 AM, ron minnich wrote: > On Thu, Nov 6, 2014 at 6:37 AM, Peter Stuge wrote: > > Ron, > > > > ron minnich wrote: > >> pose the question absent any thought to what might happen at some > >> future time? > > > > I think coreboot has had BY FAR enough of thoughtless actio