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WBR, Igor
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Hello Toan,
Wednesday, March 14, 2018, 10:13:13 AM, you wrote:
TLm> I'm so sorry if this question does not really relate to
TLm> Coreboot. But I'm facing a serious problem and trying to get help
TLm> from you who have excellent knowledge about BIOS and HW.
I'll answer just this one time.
Please
Hello Konrad,
Sunday, January 21, 2018, 9:29:35 PM, you wrote:
KE> Hi Igor, I know your work and I want to give kudos to you. However without
being
KE> kritical (it is just like that) I want to note the tips you read i.e. at
winraid.com
KE> really make you just more confused - eather they are
Hello Konrad,
Sunday, January 21, 2018, 3:12:07 PM, you wrote:
KE> You can probably set the DCI enable bit in the PCH softstraps in the
KE> descriptor, no need to mess with the BIOS editing. It seems to be bit 17
KE> in strap 0, right next to the HAP bit:
KE> value="0x1" offset="0x0" bitfield
Hello Konrad,
Sunday, January 21, 2018, 9:02:30 AM, you wrote:
KE> I would like to control the DCI and Debug bits in the boot process
KE> and dont want to mess with the AMI bios patching.
You can probably set the DCI enable bit in the PCH softstraps in the
descriptor, no need to mess with the B
Hi Ron,
Thursday, January 18, 2018, 6:54:49 PM, you wrote:
rm> Anybody out there know of an x86 emulation validation suite?
There's test-i386.c in QEMU which seems to be quite complete.
I also found a paper "Design and Testing of a CPU Emulator" from
MS Research[1]. The mentioned Giano emulator
Hi Gergely,
>Понедельник, 4 декабря 2017, 13:45 +01:00 от Gergely Kiss
>:
>
>Hi,
>
>I'm working on porting Coreboot to the ASUS AM1I-A motherboard and I'm a bit
>stuck.
>
>I could successfully build Coreboot but after flashing the ROM, my board looks
>to be bricked...
>
>Once powering on the
Hello Enrico,
Thursday, November 30, 2017, 6:54:50 PM, you wrote:
EWmIc> Can we completely replace UEFI w/o any signatures ?
Yes, unless your PC uses Boot Guard (so far it's been only enabled in
a small percentage of enterprise laptops because it ties together CPU and PCH -
you can't replace one
Hello Taiidan,
Saturday, November 11, 2017, 12:11:56 AM, you wrote:
Tgc> Hi! how can I verify the non-execution of option roms? I recently
Tgc> noticed that I had somehow turned that on with one of my latest compiles
Tgc> (without yabel secure mode either)
You can't really prove a negative, so
Hello Robert,
Wednesday, November 8, 2017, 3:36:16 PM, you wrote:
RW> 2) About proprietary BIOS
RW> Is it possible to download a "full" BIOS (with descriptor, me,
RW> ...), like it is stored on the mainboard flash chip?, because on
RW> the lenovo support webpage I can only find BIOS-Updates, with
Hello Nico,
Monday, August 7, 2017, 2:16:05 PM, you wrote:
NH> Hi Philipp,
NH> On 05.08.2017 21:58, Philipp Stanner wrote:
>> Do we have any idea what exactly they do to update the firmware internally?
NH> Well, I don't. Though, the flash chip is usually only partially
NH> protected (something
Hello Philipp,
Saturday, August 5, 2017, 8:41:42 PM, you wrote:
PS> Yes, you're probably right.
PS> Though I wonder when and how they programmed the firmware. Before or
PS> after soldering?
Most likely before, unless they have some debug header exposed. From
[1]:
> When the hardware and softwa
Hello Philipp,
Saturday, August 5, 2017, 6:01:04 PM, you wrote:
PS> PS: Rantmode: Why the hell don't they just solder a socket? It's not
PS> that unrealistic that someone bricks the BIOS while updating the
PS> firmware from time to time. Being able to replace the ROM with a fresh
PS> one is a huge
Hello ron,
Friday, June 30, 2017, 6:25:06 AM, you wrote:
rm> there's something I am certain I don't understand about SMM on intel
chipsets.
rm> The question is pretty simple. Consider a system with a recent
rm> intel chipset and flash. Is there some special secret sauce that
rm> disables writing
Hello Trammell,
Thursday, May 11, 2017, 5:42:38 PM, you wrote:
TH> On Thu, May 11, 2017 at 10:30:48AM -0500, Allen Krell wrote:
>> [...] There are multiple keys
>>
>> ME - public/private key pair - Fused in by Intel and checked by Intel
>> silicon - Probably different across models
It's a littl
Hi Allen,
Thursday, May 11, 2017, 2:01:47 PM, you wrote:
AK> One thing I am still confused about is the relationship between
AK> Intel Boot Guard and the regions of flash. My understanding is
AK> that Boot Guard only applies to the legacy BIOS region of flash,
AK> not the ME/AMT region. Is that
Hello Denis,
Tuesday, May 2, 2017, 2:13:13 AM, you wrote:
DGC> On Tue, 25 Apr 2017 22:38:15 +0800
DGC> Shawn wrote:
>> slide:
>> https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf
>>
>> video:
>> https://www.youtube.com/watch?v=2_aokrfcoUk
>>
DGC> Thanks a lot! This is very in
Hello Zoran,
Wednesday, April 5, 2017, 5:03:33 PM, you wrote:
ZS> To Coreboot,
ZS> http://www.uefi.org/sites/default/files/resources/UPFS11_P4_UEFI_GOP_AMD.pdf
ZS> Please, read about GOP, and what GOP suppose to be.
ZS> So, GOP actually need to replace vBIOS, VBT, legacy INT 10H, and
ZS> compl
Hello Patrick,
Tuesday, April 4, 2017, 8:54:09 PM, you wrote:
PR> VBT is documented by intel-gpu-tools. There's intel_vbt_decode
PR> (former intel_bios_decode) available
PR>
https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/tree/tools/intel_vbt_decode.c
PR> that will print all tables in huma
Hello ron,
Wednesday, April 5, 2017, 5:16:33 PM, you wrote:
rm> Zoran, given that we still see _MP_ and even $PIR tables in BIOS,
rm> is it possible that VBT might always be there even if it's not strictly
needed?
rm> How do non-EFI kernels get information about video if not via the VBT?
int 1
ps://01.org/linuxgraphics/gfx-docs/drm/ch04s02.html
[4] https://en.wikipedia.org/wiki/Video_Electronics_Standards_Association
thanks
ron
On Tue, Apr 4, 2017 at 10:19 AM Igor Skochinsky via coreboot
wrote:
Hello Zoran,
Monday, April 3, 2017, 8:58:43 PM, you wrote:
VBT should fulfill this VBE standard, as my best u
is no public description of these tables' layout and contents, only Intel knows
how to build and parse them.
Both VBE(code) and VBT (data) may be present in the video card's option ROM, I
guess that's the only common part.
Zoran
On Mon, Apr 3, 2017 at 7:36 PM, Igor Skochins
Hello Zoran,
Monday, April 3, 2017, 9:24:41 AM, you wrote:
> VBT is not code, it's a table -- that's what the T is -- and you can create
> it any way you want.
Not going to say more, anyway. Just to point to the standard:
https://en.wikipedia.org/wiki/VESA_BIOS_Extensions
Not sure why you po
Hello Taiidan,
Tuesday, March 7, 2017, 6:23:37 AM, you wrote:
Tgc>Uhh thanks but that's kinda missing the point of this - that I
Tgc>don't want binaries from random people on the internet.
Alas, the 8duj28us.exe update and a few others I checked do not seem to contain
the ME region or the descr
this thread. I am last 3 days very busy. Very very busy,
>>but, certainly, I'll get free time, and will explore this opportunity, since
>>it makes my old, not so sharp anymore eyes very wide!
>>
>>Thank you all,
>>Zoran
>>
>>On Wed, Feb 8, 2017 at 10:
Title: Re: [coreboot] Back to original BIOS
P.S.
Hello Michal,
The T400 BIOS is in a Pre-UEFI Phoenix FFV format. You can use phoenix_extract.py[1] to extract modules from it.
To go back to Lenovo BIOS you can try the following:
1) download an update from lenovo (e.g. 7uuj49us.exe)
2) unp
Title: Re: [coreboot] Back to original BIOS
Hello Michal,
The T400 BIOS is in a Pre-UEFI Phoenix FFV format. You can use phoenix_extract.py[1] to extract modules from it.
To go back to Lenovo BIOS you can try the following:
1) download an update from lenovo (e.g. 7uuj49us.exe)
2) unpack it wit
Hello Timothy,
Wednesday, January 25, 2017, 6:32:29 PM, you wrote:
TP> -BEGIN PGP SIGNED MESSAGE-
TP> Hash: SHA1
TP> On 01/25/2017 11:26 AM, Aaron Durbin wrote:
>> On Wed, Jan 25, 2017 at 11:24 AM, Timothy Pearson
>> wrote:
>> On 01/24/2017 10:55 PM, taii...@gmx.com wrote:
> I know
Hello bancfc,
Friday, December 23, 2016, 9:13:16 PM, you wrote:
boo> Hi,
boo> Seeing that many of you know a lot about Intel's ME I wanted to ask a
boo> couple of things if its ok.
boo> * Is the ME network accessible on all Intel chips or only the vPro ones
boo> with AMT?
IIRC there were some
Title: Re: [coreboot] Disassembly of coreboot binaries
Hello Himanshu,
Wednesday, December 14, 2016, 10:11:57 AM, you wrote:
Hi,
I am working on a hypvervisor and am using coreboot + FILO as guest BIOS. While things were fine a while back, it has stopped working. I see that my hypervisor c
Hello Nico,
Saturday, November 26, 2016, 6:42:40 PM, you wrote:
NH> Hey coreboot folks,
NH> here's something that's bugging me for a long time: Our lack of an out-
NH> of-the-box booting experience.
NH> All our payloads that don't implement legacy boot facilities (i.e. BIOS,
NH> UEFI), only work
Hi Andreas,
Tuesday, November 8, 2016, 9:07:43 PM, you wrote:
AG> On 08.11.2016 20:04, Aaron Durbin via coreboot wrote:
>> You'll need a debug version of FSP so that you can see the serial
>> messages it spits out as to why things are failing. Talk to Intel to
>> get help as that's about the best
Hi Nicola,
Nice work! I would like to add some comments inline.
Friday, November 4, 2016, 10:20:24 PM, you wrote:
NC> * Sandy Bridge boots successfully without a good FPT (but with a valid
FTPR),
NC> so it probably has a "backup" on-chip FPT. The system boots fine and
doesn't
NC> powe
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