[coreboot] Re: Multi domain PCI resource allocation: How to deal with multiple root busses on one domain

How about this option? Instead of one (coreboot) PCIe domain per (Xeon-SP) PCIe stack, we do one (coreboot) PCIe domain per root bus assignment. Regarding resource windows, we could adjust the remaining windows after assignment for a PCIe domain is completed. Jonathan From: Arthur Heymans Dat

[coreboot] coreboot for Intel Xeon server processor

Hi colleagues, I am glad to announce that coreboot for Intel Xeon server processor has reached a major milestone: it is ready for the general development communities to have fun with. The FSP/coreboot/LinuxBoot stack for OCP (Open Compute Project) DeltaLake server was accepted by OCP OSF (Open

[coreboot] Re: Intel CBnT tooling and dealing with NDA

Regarding Intel approval of the content, We (Facebook) has been working with Intel to get this moved forward as soon as possible. Thanks, Jonathan From: Patrick Georgi via coreboot Reply-To: Patrick Georgi Date: Tuesday, February 9, 2021 at 2:40 AM To: Arthur Heymans Cc: coreboot Subject: [c

[coreboot] Re: Reserve Device DRAM

Check this example: ce0e2a0140 drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region From: Rocky Phagura via coreboot Reply-To: Rocky Phagura Date: Sunday, January 3, 2021 at 10:45 PM To: "coreboot@coreboot.org" Subject: [coreboot] Re: Reserve Device DRAM Hello, Can anyone provide

[coreboot] OS driver access to FW reserved region

Hi, FW reserved regions are needed for OS to access FW data such as ACPI APEI (ACPI Platform Error Interface) data. The ACPI APEI data may include previous boot error record (BERT), or error record reported through firmware runtime component (such as SMI handler). Such FW reserved region needs

[coreboot] Intel EDK2 header files

Hi coreboot colleagues, Intel EDK2 header files are needed to build coreboot that depends on FSP. So far the practice is to keep such header files under src/vendorcode/intel/edk2 directory, and each EDK2 version takes a different directory (we have uefi_2.4, UDK2015, UDK2017). Since CPX-SP FSP

[coreboot] Re: Planning the next coreboot release

Hi Patrick, Your help and dedication is much appreciated! As we (FB and its partners) successfully finished bring-up of coreboot on CooperLake-SP based 1 socket platform, we are shifting our focus to exclusively on Cooperlake-SP based platfroms, away from using Skylake-SP based TiogaPass as th