This program outputs a binary file with artecboot header and Linux kernel
that can be used with the FILO Artecboot loader.
Signed-off-by: Nathan Williams nat...@traverse.com.au
--- /dev/null
+++ util/artecimage.c
@@ -0,0 +1,200 @@
+#include stdio.h
+#include string.h
+#include unistd.h
This patch adds the device id for the Hynix HY27UF081G2A 128MB
NAND flash IC.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: lxflash.c
===
--- lxflash.c (revision 142)
+++ lxflash.c (working copy)
@@ -586,6 +586,7
This patch adds support for enabling NAND flash even if it hasn't
been set up by coreboot. Since DIVIL_LBAR_FLSH[x], NANDF_DATA
and NANDF_CTL are likely to be incorrect, they can be specified
in Kconfig as well.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: Config.in
This patch adds a fallback command line in case the autoboot
command line fails. This could be used on an AMD Geode board to
try booting a kernel off IDE, before falling back to NAND flash.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: main/filo.c
On Sat, 2011-03-26 at 22:09 -0700, Philip Prindeville wrote:
Hi.
I'm seeing the following... When rebooting from Linux, Linux shuts down and I
see machine restart. then the grub prompt, grub eventually tries to load
something, but seems to fail, and I see the Coreboot messages, then I see
On Sun, 2011-03-27 at 16:09 -0700, Philip Prindeville wrote:
Is there a link to an image for the board (and flashing directions) on your
website?
No, there isn't. Which SST chip do you have? 49LF080A or 49LF004B?
I can send you an image off list.
Flashing instructions are to use flashrom
When using Artec loader and no file system, use dev_name for initrd
instead of flashb.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: fs/filesys.h
===
--- fs/filesys.h(revision 140)
+++ fs/filesys.h
load_linux_kernel() checks using_devsize, so we need to
clear it if we are using Artec loader without a file
system.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: i386/artecboot.c
===
--- i386/artecboot.c(revision
Trivial fix to remove compiler warning
src/northbridge/amd/lx/raminit.c:302: warning: ‘spd_byte’ may be used
uninitialized in this function
Signed-off-by: Nathan Williams nat...@traverse.com.au
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 7240898
Peter Stuge wrote:
Please see the attached patch. I would like to especially ask those
who have worked on boards which use the 5536 to check if maybe their
board should select a different POWER_BUTTON_* now. Again, existing
behavior should be unchanged from previous except on ALIX.1.
Please
On Mon, 2010-08-30 at 18:52 -0700, Warren Turkal wrote:
BTW, is there a git tree that is maintained and up to date? I'd rather
not use git svn if I could avoid it.
Thanks,
wt
Hi Warren,
I have a hourly cron job keeping this git tree updated:
git://github.com/ngwill/coreboot.git
Regards,
On 20/05/2010 10:56 PM, Kevin O'Connor wrote:
On Thu, May 20, 2010 at 03:04:01PM +1000, Nathan Williams wrote:
On 20/05/2010 11:23 AM, Nathan Williams wrote:
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Currently I'm having 4
On 20/05/2010 3:04 PM, Nathan Williams wrote:
1. On initial power-on, SeaBIOS doesn't get past Press F12 for boot menu.
...
3. Rev 5476 introduces a test for CS5536, which is failing
Peter Stuge has been helping me on IRC to investigate this issue. We think
the key is that for some reason
On 20/05/2010 10:56 PM, Kevin O'Connor wrote:
On Thu, May 20, 2010 at 03:04:01PM +1000, Nathan Williams wrote:
On 20/05/2010 11:23 AM, Nathan Williams wrote:
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Currently I'm having 4
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: src/mainboard/Kconfig
===
--- src/mainboard/Kconfig (revision 5573)
+++ src/mainboard/Kconfig (working copy
On 20/05/2010 11:23 AM, Nathan Williams wrote:
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Currently I'm having 4 issues with coreboot-v4 on this board:
1. On initial power-on, SeaBIOS doesn't get past Press F12 for boot menu
On 20/05/2010 3:04 PM, Nathan Williams wrote:
2. Minor issue with valid_area() in src/boot/selfboot.c
I have a temporary workaround for this one where I simply return 1 and skip
the test that would otherwise fail.
I've just realised that this one has been fixed recently, so I don't need
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: src/mainboard/digitallogic/msm800sev/devicetree.cb
===
--- src/mainboard/digitallogic/msm800sev/devicetree.cb (revision 5521)
+++ src/mainboard/digitallogic/msm800sev
On 5/05/2010 12:15 AM, Stefan Reinauer wrote:
On 5/4/10 10:07 AM, Nathan Williams wrote:
Signed-off-by: Nathan Williams nat...@traverse.com.au
-device pci 1.0 on end
-device pci 1.1 on end
+device pci 1.0 on end # Northbridge
Marc Jones wrote:
On Fri, Nov 27, 2009 at 2:05 AM, Nathan Williams nat...@traverse.com.au
wrote:
Nathan Williams wrote:
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
Nathan Williams wrote:
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed
Peter Stuge wrote:
Nathan Williams wrote:
AMD NAS:
http://coreboot.pastebin.com/m53aed60b
If you want to unclutter output a little, you can wipe the 5536 MSRs
from the file after the first run. msrtool only considers the MSRs
that are explicitly listed in the input file when run with -d
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it
with coreboot:
http
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it with
coreboot:
http://coreboot.pastebin.com/m39b22c21
The only differences I can see are related to interrupts, which
Marc Jones wrote:
On Tue, Nov 10, 2009 at 1:26 PM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au
wrote:
Another observation I made was that by setting the debug_level to
BIOS_CRIT,
instead of dying
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au wrote:
Another observation I made was that by setting the debug_level to BIOS_CRIT,
instead of dying at the usual spot in disable_car() and stopping, coreboot
would reset continuously (cycling every 1-2
Building grub2 was failing if the symlink already exists.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: buildrom-devel/packages/grub2/grub2.mk
===
--- buildrom-devel/packages/grub2/grub2.mk (revision 271
hardcode.diff was out of date and failed to apply.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: buildrom-devel/packages/seabios/hardcode.diff
===
--- buildrom-devel/packages/seabios/hardcode.diff (revision 268
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