ore intelligently.
This keeps popping up regularly.
To prevent people wasting there and your time in the future maybe
someone with wiki write rights (you?) could edit the "Will coreboot work
on my machine?" alinea in the coreboot FAQ: http://www.coreboot.org/FAQ
Greetings, Nils.
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TRR".
See attachment for part of page 494 of the GX2 databook.:)
Philip Prindeville wrote:
>Caching is bits 30:29 of CR0.
There are actually a lot more MSR registers for defining cache regions.
Thanks, Nils.
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his further after SeaBIOS Geode
VGA is ready.
Philip Prindeville wrote:
>Also, the Alix 6F2 doesn't have a keyboard controller... is there a way
>to turn off the i8042 stuff?
Those i8042 warning at the beginning before warm reset comes from
SeaBIOS.
There is a SeaBIOS kconfig
to get it right?
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ux and when you use the in kernel geode GX2 vga driver you
can use VGA.
Power button doesn't work.
No ACPI. (no real problem when you don't use suspend)
Beeper doesn't work.
Flashrom works.
If you want an experimental coreboot rom image send me a mail.
Greetings, Nils.
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Op zondag 06-11-2011 om 11:31 uur [tijdzone +0100], schreef Patrick
Georgi:
> Am Sa 05 Nov 2011 20:16:01 CET schrieb Nils:
> > I tried to test Patricks new patch "Change Id9e6b204: buildgcc:
> > Explicitely state CC everywhere" but crossgcc doesn't compile at al.
>
Hi Patrick and Stefan,
I tried to test Patricks new patch "Change Id9e6b204: buildgcc:
Explicitely state CC everywhere" but crossgcc doesn't compile at al.
The problem started after commit: "Change I1b7d5b89: buildgcc: Update
coreboot reference toolchain to gcc 4.6.2"
Op dinsdag 01-11-2011 om 20:13 uur [tijdzone +0100], schreef Patrick
Georgi:
> Am 29.10.2011 22:34, schrieb Nils:
> > CC wasn't set and bison and flex were not instaled.
> >
> > The acpica-unix-20110922/README states that the Makefiles contain
> > CC = gcc but on
lex.
Signed-off-by: Nils Jacobs
Thanks, Nils.
--- acpica-unix-20110922/compiler/Makefile
+++ acpica-unix-20110922/compiler/Makefile
@@ -19,6 +19,7 @@
HOST = _LINUX
NOMAN = YES
+CC =gcc
COMPILE = $(CC) -c $(CFLAGS) $(CWARNINGFLAGS) -o$@ $<
ACPICA_COM
pprove
it
Maybe because i have a new mail address.
Thanks, Nils.
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tracking system does not seem to know msrtool.
Thanks, Nils.
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Hi Andrew,
As i understand it the description of the problem belongs to the
previous V2 version of the VGA patch witch this V3 version (at the
bottom off the tread) together with the mode hack patch (little patch to
vgatables.c) addresses.
Thanks, Nils.
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ent state for inclusion in Seabios.
Thanks, Nils.
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o windows will probably not
work.
Greetings, Nils.
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>Unfortunately the updated repo r6468 gives exactly the same error output on
>my
>computer.
>
>More suggestions?
To clarify this a little:
This command works:
nils@debian:~/hello$ /home/nils/libpayload/install/libpayload/bin/lpgcc -o
hello.elf hello.c
And the basename error s
gives exactly the same error output on my
computer.
More suggestions?
Thanks, Nils.
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Update repo path in libpayload readme.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: README
===
--- README (revision 6468)
+++ README (working copy)
@@ -14,7 +14,7 @@
Installation
- $ svn co svn://coreboot.org
ibpayload sample:
>make
It seems not to work that way on my Debian system.
Following the readme i only downloaded libpayload and put my example file
(hello.c + makefile) in the directory "/hello" :
nils@debian:~$ svn co svn://coreboot.org/repos/trunk/payloads/libpayload
Alibpayloa
ot;
See:
https://bugzilla.redhat.com/show_bug.cgi?id=227657
https://bugzilla.redhat.com/show_bug.cgi?id=205520
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hello all,
After building and installing libpayload i tried building the test program
hello.c .
Unfortunately i got a (error?) message:
nils@debian:~/hello$ /opt/libpayload/bin/lpgcc -o hello.elf hello.c
basename: missing operand
Try `basename --help' for more information.
Is this something
Hello All,
I have a rom image witch contains an JCALG1 archive.
I would like to know what it contains , does anyone know of a ready to use
tool that can extract an JCALG1 archive?
Thanks, Nils.
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> {
>print_emerg("DIE\n");
>/* this guarantees we flush the UART fifos (if any) and also
Should this change also be applied for the almost same function in Geode GX2?
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Hi Scott and Stefan,
Scott wrote:
> Hello Nils,
>
> If I build ts5300 using xgcc 4.5.1, I get:
>
> Fixed space: 0xe05b-0x1 total: 8101 slack: 2 Percent slack: 0.0%
> 16bit size: 38896
> 32bit segmented size: 2416
> 32bit flat size: 51424
00 Free space: 57072 Percent used: 56.5% (128KiB rom)
>
> Thanks,
> Scott
Thanks for your answer.
Which coreboot revision and board did you use?
Is that the technologic/ts5300 which gives me trouble?
Are these numbers including SeaBios which is nowadays automatically included
as payloa
systems
the crosgcc is useless as reference.
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tion between bios-vgabios-vgaregisters-pcibars?
Thanks, Nils.
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?
>
>Yup, thanks! r6275
Thanks for the review and committing.
Nils.
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Hi Stefan,
Op woensdag 19 januari 2011 07:56:53 schreef u:
> * Nils [110113 15:42]:
> > Add Geode GX2 memmory descriptors.
> > Add a simple README file.
> >
> > Signed-off-by: Nils Jacobs
> >
> > Thanks, Nils.
>
> Thanks, r6274
Thanks for the
Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs
This patch is buid and boot tested.
Hi Peter,
You wrote:
>>
>> +config VIDEO_MB
>> + int
>> + default 8
>> + depends on NORTHBRIDGE_AMD_GX2
>> +
>
>Acke
OK i have done some more hours of building and testing.
After i do buildgcc there is no .xcompile file.
After doing make menuconfig i have the following .xcompile file:
|nils@debian:~/coreboot_6255$ cat .xcompile
|# elf32-i386 toolchain
|AS:=/home/nils/coreboot_6255/util/crossgcc/xgcc/bin/i386
dgcc
this builds xgcc in coreboot/util/crossgcc
no .xcompile
i have tried:
in coreboot dir
/home/nils/coreboot/util/crossgcc/buildgcc
this builds xgcc in coreboot dir
but no .xcompile
I could not find any documentation on how to use this.
It would be nice if someone could shed some light
Hi Stefan,
You wrote:
>It doesn't occur with the coreboot toolchain iirc though
I did a fresh unmoddified checkout on r6255.
Then i did buildgcc.
The downloading/building of this beast takes more than an hour on my old
laptop. :)
Then i got the same result:
nils@debian:~/coreboot_62
)
Could not add the file to CBFS, it's probably too big.
File size: 46723 bytes (45 KB).
make: *** [coreboot-builds/technologic_ts5300/coreboot.rom] Fout 1
Is this a known problem?
Thanks, Nils.
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am doing something stupid but
maybe someone could give me any advise on how to debug this further.
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Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: geodegx2.c
===
--- geodegx2.c (revision 6228)
+++ geodegx2.c (working copy)
@@ -26,6 +26,592 @@
}
const struct msrdef
-update gx2/northbridgeinit.c to lx standards
-remove not longer needed code from gx2/northbridge.c
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/northbridge/amd/gx2/northbridge.c
===
--- src/northbridge/amd/gx2
For gx2/northbridgeinit.c
-some white space fixes
-some codingstyle fixes
-some comment fixes.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/northbridge/amd/gx2/northbridgeinit.c
===
--- src/northbridge/amd/gx2
Hello all,
Here comes the next round of patches for Geode GX2.
This patch set is ABUILD and boot tested on my Wyse S50 .
The second patch depends on the first one to cleanly apply.
Thanks, Nils.
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I wrote:
> Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge
> code and fix CIS mode comments.
>
> Signed-off-by: Nils Jacobs
>
> V2: Add a extra comment.
> V3: Remove already commited part.
>
> Thanks, Nils.
This can be dropped, Stefan alre
Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.
Signed-off-by: Nils Jacobs
V2: Add a extra comment.
V3: Remove already commited part.
Thanks, Nils.
Index: src/southbridge/amd/cs5535/early_setup.c
meone could ack and commit my patch :
> "[coreboot] [PATCH 4/6 V2] Geode GX2 cleanup patch" from Mon 27 Dec.
> We could get rid of this build error.
>
> And maybe also:
> "[coreboot] [PATCH 3/6 V2] Geode GX2 cleanup patch"
>
> Thanks, Nils.
It seems
rthbridge code to match Geode LX code.
> > -Add missing copyright header to northbridge.c.
> > -Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
> >
> >
> > Signed-off-by: Nils Jacobs
> > Acked-by: Myles Watson
>
> Any idea why this broke t
rom Mon 27 Dec.
We could get rid of this build error.
And maybe also:
"[coreboot] [PATCH 3/6 V2] Geode GX2 cleanup patch"
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Change the print_conf activation from >=BIOS_ERR to >=BIOS_DEBUG.
Signed-off-by: Nils Jacobs
Op donderdag 30 december 2010 02:44:12 schreef u:
> On Wed, Dec 29, 2010 at 4:46 PM, Nils wrote:
> > Op woensdag 29 december 2010 21:44:08 schreef u:
> >> On Wed, Dec 29, 2010
Op woensdag 29 december 2010 21:44:08 schreef u:
> On Wed, Dec 29, 2010 at 12:04 PM, Nils wrote:
> > Add a MSR printing function to northbridge.c like in the Geode LX code.
>
> It's surprising to have it included
>
> +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_E
Hi Myles,
Thanks for reviewing and committing my patches.
Op woensdag 29 december 2010 21:42:39 schreef u:
> On Wed, Dec 29, 2010 at 12:05 PM, Nils wrote:
> > Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
>
> There's also an added init function for the
-Clean up some comments.
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/southbridge/amd/cs5535/cs5535.h
===
--- src/southbridge/amd/cs5535/cs5535.h
Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/mainboard/wyse/s50/irq_tables.c
===
--- src/mainboard/wyse/s50/irq_tables.c (revision 6218)
+++ src/mainboard/wyse
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/northbridge/amd/gx2/northbridge.c
===
--- src/northbridge/amd/gx2
Delete some unused code.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/northbridge/amd/gx2/northbridge.c
===
--- src/northbridge/amd/gx2/northbridge.c (revision 6218)
+++ src/northbridge/amd/gx2/northbridge.c (working copy
-Remove the AES register names.(GX2 has no AES registers)
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/include/cpu/amd/gx2def.h
===
--- src/include/cpu/amd/gx2def.h (revision 6218)
+++ src/include/cpu/amd/gx2def.h (working
Add a MSR printing function to northbridge.c like in the Geode LX code.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/southbridge/amd/cs5535/cs5535.h
===
--- src/southbridge/amd/cs5535/cs5535.h (revision 6218)
+++ src
-by: Nils Jacobs
Thanks, Nils.
Index: src/include/cpu/amd/gx2def.h
===
--- src/include/cpu/amd/gx2def.h (revision 6218)
+++ src/include/cpu/amd/gx2def.h (working copy)
@@ -77,7 +77,6 @@
#define GL1_GLCP 3
#define GL1_PCI 4
#define
Hello all,
Here comes the next round of split up and updated patches for Geode GX2.
This patch set is ABUILD and boot tested on my Wyse S50 in combination with
the 2 not yet committed patches from the previous round.
Thanks, Nils.
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Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.
Signed-off-by: Nils Jacobs
V2: Add a extra comment.
Thanks, Nils.
Index: src/southbridge/amd/cs5535/early_setup.c
===
--- src
updated patch with this extra comment for future readers.
>FG_GIO_MSR_SEL is defined
>to MSR_FG + 0x2010 above, so this particular change changes which MSR
>is being accessed. Is on purpose?
Yes.(see above)
Thanks, Nils.
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Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs
This was suggested by Peter and Stefan. Thanks!
I also included the same patch for Geode LX and added a second die()
to Geode GX2 at the same place as in the LX code.
I boot tested it on my Wys
Stefan wrote:
>On 26.12.2010, at 06:19, Peter Stuge wrote:
>
>> Nils wrote:
>>> -__asm__ __volatile__("hlt\n");
>>> +while(1) {
>>> +__asm__ __volatile__("hlt\n");
>>> +}
>>
>> Why
Patrick:
Thanks for the quick ack.
All:
It would be nice if someone with SVN access would be able to commit these
patches.
Thanks, Nils.
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Move VIDEO_MB to Kconfig.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/northbridge/amd/gx2/Kconfig
===
--- src/northbridge/amd/gx2/Kconfig (revision 6205)
+++ src/northbridge/amd/gx2/Kconfig (working copy)
@@ -21,6 +21,11
Delete some unused code.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/cpu/amd/model_gx2/cpureginit.c
===
--- src/cpu/amd/model_gx2/cpureginit.c (revision 6205)
+++ src/cpu/amd/model_gx2/cpureginit.c (working copy)
@@ -4,8
Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/southbridge/amd/cs5535/early_setup.c
===
--- src/southbridge/amd/cs5535
Add a "while (1)" function around the hlt instruction to assure the
processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs
This was suggested by Uwe Hermann. Thanks!
I also included the same patch for Geode LX.
Nils.
Index: src/northbridge/amd/
Replace some MSR register numbers with names.
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/include/cpu/amd/gx2def.h
===
--- src/include/cpu/amd/gx2def.h (revision 6205)
+++ src/include/cpu/amd/gx2def.h (working copy
Hello all,
I finally had a little time to work on further splitting up and updating my
patches for Geode GX2.
This patch set is ABUILD and boot tested on my Wyse S50.
Thanks, Nils.
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Sorry i pushed the wrong button.
Disregard my last mail for now.
Thanks, Nils.
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Move VIDEO_MB to Kconfig.
Signed-off-by: Nils Jacobs
Thanks, Nils.
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Op vrijdag 5 november 2010 01:29:52 schreef u:
> On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote:
> > >Shouldn't there be a "while (1)" around the hlt instruction?
> >
> > ?? i don't know should it?
> > The code seems to work, but if it i
Op vrijdag 5 november 2010 01:20:03 schreef u:
> On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote:
> > This patch defines the unused DIMM1 to 0xFF to make it obvious it is a
> > bogus value.
> >
> > Signed-off-by: Nils Jacobs
>
> Thanks, r6022. I added som
Op vrijdag 5 november 2010 01:23:48 schreef u:
> On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote:
> > This patch adds Kconfig cpu speed selection to Geode GX2 boards as
> > requested by Uwe.
> >
> > Signed-off-by: Nils Jacobs
>
> Thanks, r6023.
>
Op vrijdag 5 november 2010 01:14:03 schreef u:
> On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote:
> > Remove banner wrapper function and unify print(k).
> >
> > Signed-off-by: Nils Jacobs
>
> Thanks, 6021.
>
>
> Uwe.
Thanks for the review and commi
Remove banner wrapper function and unify print(k).
Signed-off-by: Nils Jacobs
The banner part was requested by Uwe.
This is Abuild and boot tested.
V2:Also change Assymetirc into Asymmetric thanks to Idwer for spotting.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
Remove banner wrapper function and unify print(k).
Signed-off-by: Nils Jacobs
The banner part was requested by Uwe.
This is Abuild and boot tested.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
===
--- src/northbridge
Uwe wrote,
Op woensdag 3 november 2010 14:24:47 schreef u:
> Thanks, r6016.
Thanks for the fast review and commit.
Nils.
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Hi Uwe,
Op woensdag 3 november 2010 14:23:36 schreef u:
>Thanks, r6015
Thanks for the fast review and commit.
> "Clean up stuff" looks better than "This patch cleans up stuff" in svn
> logs.
OK will do better next time.
Thanks, Nils.
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Op woensdag 3 november 2010 14:20:31 schreef u:
> Thanks, r6014 with some further cosmetic fixes I noticed.
>
>
> Uwe.
Thanks for the fast review and commit.
Nils.
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Hi all,
Could someone explain the difference between printk(BIOS_EMERG, "message\n")
and print_emerg("message\n") and witch one is preferred?
Thanks, Nils
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This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by
Uwe.
Signed-off-by: Nils Jacobs
This is Abuild and boot tested.
Thanks, Nils.
Index: src/mainboard/wyse/s50/Kconfig
===
--- src/mainboard/wyse/s50
This patch removes some unused code from gx2/raminit.c .
Signed-off-by: Nils Jacobs
This is Abuild and boot tested.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
===
--- src/northbridge/amd/gx2/raminit.c (revision 6011
This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus
value.
Signed-off-by: Nils Jacobs
This was requested by Myles.
This is Abuild and boot tested.
Thanks, Nils.
Index: src/mainboard/wyse/s50/romstage.c
This patch cleans up some more comments and white space in
model_gx2/cpureginit.c .
Signed-off-by: Nils Jacobs
This is Abuild and boot tested.
Thanks, Nils.
Index: src/cpu/amd/model_gx2/cpureginit.c
===
--- src/cpu/amd/model_gx2
This patch cleans up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.
Signed-off-by: Nils Jacobs
This is Abuild and boot tested.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
===
--- src
.
When i finish my GX2 updating i will send a patch to update gplvsa to make both
LX and GX2 blobs and supply the working result blob.
Thanks, Nils.
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when i find some time.
>Shouldn't there be a "while (1)" around the hlt instruction?
?? i don't know should it?
The code seems to work, but if it is preferred/needed i will add it.
Can you point me to some example code or could you supply some code snipped i
can test?
This patch series splits up the Geode GX2 auto DRAM detect patch into 4
patches as requested.
It should be easy to review now.
The patches are Abuild and boot tested on my Wyse S50 .
They should be applied in this order.
Thanks, Nils.
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This patch removes some unused code.
Signed-off-by: Nils Jacobs
Index: src/northbridge/amd/gx2/pll_reset.c
===
--- src/northbridge/amd/gx2/pll_reset.c (revision 6006)
+++ src/northbridge/amd/gx2/pll_reset.c (working copy)
@@ -24,69
)
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/include/cpu/amd/gx2def.h
===
--- src/include/cpu/amd/gx2def.h (revision 6006)
+++ src/include/cpu/amd/gx2def.h (working copy)
@@ -412,6 +412,13 @@
#define AES_GLD_MSR_PM (MSR_AES
This patch cleans up some white space and comments.
It also adds a copyright header to pll_reset.c .
Signed-off-by: Nils Jacobs
Thanks, Nils.
Index: src/include/cpu/amd/gx2def.h
===
--- src/include/cpu/amd/gx2def.h (revision 6006
This patch changes the MSR register numbers in to more descriptive names.
Signed-off-by: Nils Jacobs
Thanks, Nils
Index: src/northbridge/amd/gx2/raminit.c
===
--- src/northbridge/amd/gx2/raminit.c (revision 6006)
+++ src
I am happy to see there is still some interest in GX2 patches.
I will try to split the patch up in 2-3 patches.
Unfortunately i will probably have very little time for hobby next week so it
can take a while.
Thanks, Nils.
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r the long rant.
I won`t bother you any longer.
Thanks,Nils.
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lds ok so its fine with me.
Should i redo the patch for that?
Thanks, nils.
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gx2/raminit.c:431: error: ‘DIMM1’ undeclared (first use in
this function)
src/northbridge/amd/gx2/raminit.c: In function ‘sdram_set_spd_registers’:
src/northbridge/amd/gx2/raminit.c:482: error: ‘DIMM1’ undeclared (first use in
this function)
make: *** [build/mainboard/wyse/s50/romstage.pre.inc] Fout 1
***Ping***
It would be nice if someone finds the time to ack/commit or comment my patch.
On 10/7/10 , Nils wrote:
>This patch brings the adapted Geode LX auto DRAM detect code to GX2 ,
>cleans up some files and adds a processor speed setting function in human
>readable Mhz.
>
&g
This patch brings the adapted Geode LX auto DRAM detect code to GX2 ,
cleans up some files and adds a processor speed setting function in human
readable Mhz.
Signed-off-by: Nils Jacobs
It is Abuild and boot tested on my Wyse S50 with 3 different SODIMMs (128Mb
pc2700, 256Mb pc2100, 512Mb
or should be unchanged from previous except on ALIX.1.
I tested your patch on the Wyse S50 (r5901) and it seems to work ok.
So:
Acked-by: Nils Jacobs
Thanks, Nils.
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nds (europe)?
Nils.
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Stephan wrote:
>Signed-off-by: Stefan Reinauer
>
>for the below:
>
>svn rm src/mainboard/olpc
>
>plus
>
>Index: src/mainboard/Kconfig
Acked-by: Nils Jacobs
Thanks,Nils.
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boards and give me the DRAM types?
Thanks, Nils.
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Hi Warren,
I think you forgot to convert the rest of the GX2 boards. :)
(AMD Rumba, Lippert Frontrunner, OLPC btest and OLPC rev_a)
And when you are at it should ARCH_X86 and UDELAY_TSC also
be moved?
Thanks, Nils.
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