> On Monday, February 17, 2014 06:27:34 AM Oskar Enoksson wrote:
>> On 02/16/2014 09:08 AM, mrnuke wrote:
>> > On Sunday, February 16, 2014 08:40:43 AM Oskar Enoksson wrote:
>> >> Ok, but when I look inside my DL145G1 the text "AMD Serenade" is
>>
On 02/16/2014 09:08 AM, mrnuke wrote:
> On Sunday, February 16, 2014 08:40:43 AM Oskar Enoksson wrote:
>> Ok, but when I look inside my DL145G1 the text "AMD Serenade" is printed
>> on the motherboard. In fact, HP DL145 G1 is not a motherboard, it's a
>>
> We've gotten away from just saying "this is like that so it must work."
>
> Run the script. That's the requirement now.
>
> ron
>
>
> On Thu, Feb 13, 2014 at 5:23 AM, Oskar Enoksson <mailto:e...@lysator.liu.se>> wrote:
>
>
I noticed that "AMD Serenade" motherboard is not listed as supported.
However, supposedly that motherboard is identical to HP DL145 G1. So,
probably using the hp/dl145_g1 motherboard configuration will produce a
ROM that works with "AMD Serenade" aswell.
Are such alias motherboards handled in any
On 11/02/2011 04:31 PM, Marc Jones wrote:
On Wed, Nov 2, 2011 at 6:37 AM, Oskar Enoksson wrote:
I have a chip called CDC960 on my motherboard. It is responsible for
generating the bus frequency for the cpu, the pci bus etc. I downloaded the
datasheet and noticed that I can change the base
I have a chip called CDC960 on my motherboard. It is responsible for
generating the bus frequency for the cpu, the pci bus etc. I downloaded
the datasheet and noticed that I can change the base frequency by +/-10%
by sending an smbus command to the cdc960.
When I sent the smbus commands from a
On 10/20/2011 02:30 PM, Christoph Grenz wrote:
Am Donnerstag, 20. Oktober 2011, um 05:20:11 schrieb Christoph Grenz:
Am Mittwoch, 19. Oktober 2011, um 22:52:16 schrieb Oskar Enoksson:
Your recent changes make the error messages go away.
However, I noticed another error message about PS2
Your recent changes make the error messages go away.
However, I noticed another error message about PS2 controller:
[1.543494] i8042 kbd 00:02: unable to assign resources
[1.584667] i8042 kbd: probe of 00:02 failed with error -16
[1.625694] i8042 aux 00:03: [irq 12]
[1.626460] i8
On 10/17/2011 04:24 AM, Marc Jones wrote:
On Sun, Oct 16, 2011 at 4:57 AM, Oskar Enoksson wrote:
Can someone explain what RAMINIT_SYSINFO configuration option does? I
thought I understood, but I don't.
/Oskar
Hi Oskar,
RAMINIT_SYSINFO is the config option to create the AMD sysinfo
stru
Can someone explain what RAMINIT_SYSINFO configuration option does? I
thought I understood, but I don't.
/Oskar
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I get the following warnings:
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
I2C: 01:08 missing read_resources
I2C: 04:50 missing read_resources
I2C: 04:51 missing read_resources
I2C: 04:52 missing read_resources
I2C
On 10/06/2011 06:51 PM, yhlu wrote:
On Thu, Oct 6, 2011 at 9:26 AM, Oskar Enoksson wrote:
-
+ // Test if this CPU is a Fam 0Fh rev. F or later
+ const int is_revF =
+ ((cpuid_eax(0x8001)&0x0f00)>>8>= 0xf) ||
+ (((cpuid_eax(0x800
I'm trying to make Cool'n'Quiet working on DL145G1 (dual-socket 940-pin
K8 processors) but I just get FID/VID changes on one of the CPU's (under
Linux 2.6.37).
Problem seems to be that amd_model_fxx_generate_powernow just generates
two "Processor" objects in SSDT. I think there should be one f
On 10/05/2011 12:30 AM, Marc Jones wrote:
On Tue, Oct 4, 2011 at 3:43 PM, Oskar Enoksson wrote:
On 10/04/2011 06:45 PM, Marc Jones wrote:
On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson
wrote:
I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and
got
the following error
On 10/04/2011 06:45 PM, Marc Jones wrote:
On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson wrote:
I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and got
the following error from Linux when booting:
"WARNING: BIOS bug: CPU MTRRs don't cover all of memory" lo
Thanks! This worked fine.
On 10/04/2011 07:06 PM, Peter Stuge wrote:
Hi,
Oskar Enoksson wrote:
I'm trying to upload a patch. It seems that for some reason
"gerrit" requires a "signed-off-by" line in every single local
commit in order to push it to the remote location.
I'm trying to upload a patch. It seems that for some reason "gerrit"
requires a "signed-off-by" line in every single local commit in order to
push it to the remote location. I'm able to "amend" such a line to the
very last commit, but I can't find a way to do it on the previous
commits. How can
I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and
got the following error from Linux when booting:
"WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB
of ram
(The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU socket).
After digging
Following Patricks advice I created a file
src/northbridge/amd/amdk8/bootblock.c and added the necessary config
BOOTBLOCK_NORTHBRIDGE_INIT section to src/northbridge/amd/amdk8/Kconfig.
The only thing done in my northbridge bootblock.c is calling
enumerate_ht_chain(). (I also removed that call
On 09/22/2011 07:45 PM, Oskar Enoksson wrote:
On 08/20/2010 10:39 PM, Myles Watson wrote:
Attached is a cleaned-up patch. Thanks to Myles and others for
excellent
help and support. I hope someone finds the result useful.
Rev 5723.
Thanks for contributing!
Myles
Hi. One year after
On 08/20/2010 10:39 PM, Myles Watson wrote:
Attached is a cleaned-up patch. Thanks to Myles and others for excellent
help and support. I hope someone finds the result useful.
Rev 5723.
Thanks for contributing!
Myles
Hi. One year after contributing the port to HP DL145 G1 motherboard code
I dec
On 08/20/2010 10:39 PM, Myles Watson wrote:
Attached is a cleaned-up patch. Thanks to Myles and others for excellent
help and support. I hope someone finds the result useful.
Rev 5723.
Thanks for contributing!
Myles
Hi. One year after contributing the port to HP DL145 G1 motherboard code
I dec
Oskar Enoksson wrote:
> Myles Watson wrote:
>
>>> I think Myles was right, there is a i2c mux in this server that somehow
>>> multiplexes DIMM devices on the i2c bus. I was able to guess which i2c
>>> ports contain the DIMM info, and which port is t
Carl-Daniel Hailfinger wrote:
> On 16.08.2010 21:15, Myles Watson wrote:
>
>>> The memory problem remains though. If only that can be solved, then I'm
>>> basically satisfied. Any hints?
>>>
>>>
>>>
Have you tried different configurations? Coreboot is only seeing the
RAM o
Torsten Duwe wrote:
> On Thursday 12 August 2010 21:54:49 Rudolf Marek wrote:
>
>
>> Is it pre fam10h? It was always big mystery for me how it can work ;) The
>> AP got the SAME stack... If you don't believe check for yourself.
>>
>
> Oskar seems to be succesful with the current code. Oska
Myles Watson wrote:
>
>
>> Ok thank you for all your help. I can boot and run Linux 2.6.33 now and
>> I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS
>> as payload for coreboot and it works. I also compiled and added GPXE to
>> the image and was able to PXE-boot. Howeve
Ok thank you for all your help. I can boot and run Linux 2.6.33 now and
I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS
as payload for coreboot and it works. I also compiled and added GPXE to
the image and was able to PXE-boot. However, there are a few problems:
- The serve
Myles Watson wrote:
> On Mon, Aug 9, 2010 at 8:16 AM, Myles Watson wrote:
>
>> On Sat, Aug 7, 2010 at 9:57 AM, Oskar Enoksson wrote:
>>
>>> Ok, I'm able to hotswap the BIOS chip, burn it and hot-remove it without
>>> stopping the "development
Ok, I'm able to hotswap the BIOS chip, burn it and hot-remove it without
stopping the "development server" , then moving it to the target server
and power it up (although it takes some effort to avoid bending the pins)
However I'm not getting any output whatsoever from the target server.
Nothing o
Myles Watson wrote:
> On Thu, Aug 5, 2010 at 1:58 PM, Oskar Enoksson wrote:
>
>> On 08/05/2010 08:03 PM, Myles Watson wrote:
>>
>> Thanks for responding!
>>
>> I compiled superiotool from coreboot trunk, and flashrom from the latest
>> r
On 08/05/2010 08:03 PM, Myles Watson wrote:
> On Thu, Aug 5, 2010 at 9:59 AM, Oskar Enoksson wrote:
>
>> Hello. Sorry to bother you all with a BIOS problem ...
>>
>> I have a large number of old HP DL145 G1 servers with two Opteron
>> 248 each (single core).
Hello. Sorry to bother you all with a BIOS problem ...
I have a large number of old HP DL145 G1 servers with two Opteron
248 each (single core). I want to upgrade the CPU's to Opteron 280 (dualcore).
I have tried to simply install two 280 CPU's and boot up. The BIOS bootup
process first seems to
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