Mass storage controller: Promise Technology, Inc. PDC20267
(FastTrak100/Ultra100) (rev 02)
01:00.0 VGA compatible controller: nVidia Corporation NV25 [GeForce4 Ti 4200]
(rev a3)
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Roger
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oller: NEC Corporation USB (rev 41)
02:08.1 USB Controller: NEC Corporation USB (rev 41)
02:08.2 USB Controller: NEC Corporation USB 2.0 (rev 02)
02:0b.0 FireWire (IEEE 1394): Texas Instruments TSB12LV26 IEEE-1394 Controller
(Link)
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Roger
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etree.cb
>src/mainboard/a-trend/atc-6220/devicetree.cb
>src/mainboard/azza/pt-6ibd/devicetree.cb
Using the abit/be6-ii_v2_0 target, stalled on INT10
Now this is where the fun starts, because I just accidentally flashed the ROM
instead of the BIOS Saver device. ug.
... attaching
On Wed, Dec 29, 2010 at 10:41:36AM -0900, Roger wrote:
>Which target within "make menuconfig" is best for this 440BX Intel Tyan 1832DL
>mainboard?
>
>CPU/RAM: Dual 750P3 CPU w/ 1GB RAM (4 slots)
>
>SuperIO: MEGATRENDS PC87309IBW-VLJ
>
>00:00.0 Host bridge: Intel
On Wed, Dec 29, 2010 at 09:51:55PM -0500, Keith Hui wrote:
>>
>> Believe it or not, tried my old LinuxBIOS2.0.0 build using filo on a softboot
>> (no power off, just reset) and found it booted into filo!
>>
>> Seems it's stalling at raminit on cold boots. I have a diff of logs just
>> in case anyb
. Document and post rows c0 & 60.
I'll start doing this tomorrow with 3 mix-match DIMMS and yank 3 of my 256M
Tyan DIMMS.
I'm going to guess, you don't need the sizes and slots documented corresponding
to each lspci -xxxx, as you're just going for an average?
--
Roge
On Thu, Dec 30, 2010 at 01:55:15AM -0500, Keith Hui wrote:
>raminit is able to read SPD out of the box, so that's good news. I was
>hoping to see some differences on how it sees the RAM configuration
>between cold and warm boot, but there isn't, and it did run through
>the entire raminit. If you lo
On Thu, Dec 30, 2010 at 10:45:39AM -0900, Roger wrote:
>>Here's what I got right now.
>>
>># lspci -
>>00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge
>>(rev 03)
>>60: 10 10 18 20 30 30 30 30 00 23 40 f7 03 e0 00 00
>&g
On Thu, Dec 30, 2010 at 10:15:11AM -0900, Roger wrote:
>On Thu, Dec 30, 2010 at 01:55:15AM -0500, Keith Hui wrote:
>>raminit is able to read SPD out of the box, so that's good news. I was
>>hoping to see some differences on how it sees the RAM configuration
>>between col
Attaching log of warm boot without VGA option ROMs.
On Thu, Dec 30, 2010 at 11:09:52AM -0500, Kevin O'Connor wrote:
>On Wed, Dec 29, 2010 at 11:01:37PM -0900, Roger wrote:
>> I've got Boot! ... But ...
>>
>> Using the ASUS P2B only on a warm boot, and I desele
rial console along with the quick f12 boot pause. But pressing f12 only
pauses longer with nothing else displayed via serial console. But, I can press
ESC and have it reboot, or the wonderful Windows Key will print it's scancode
on screen, but no other keys. (See very last lines
VGA is on PCI 01:00
01:00.0 VGA compatible controller: nVidia Corporation NV25 [GeForce4 Ti 4200]
(rev a3) (prog-if 00 [VGA controller])
Subsystem: Micro-Star International Co., Ltd. Device 8700
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR-
Checking out SeaBIOS 0.6.1-stable
Already up-to-date.
M src/config.h
Already on '0.6.1-stable'
/bin/sh: -Wa,--divide: command not found
Compiling whole program out/ccode.16.s
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Roger
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On Fri, Dec 31, 2010 at 11:50:18AM +0100, Stefan Reinauer wrote:
>On 31.12.2010, at 10:07, Roger wrote:
>
>> 1) If I use coreboot's "Run VGA Option ROMs", I can get VGA up and the first
>> thing displayed is one text line of something like "SeaBIOS Version..
On Fri, Dec 31, 2010 at 11:37:52AM -0500, Kevin O'Connor wrote:
>On Fri, Dec 31, 2010 at 01:54:04AM -0900, Roger wrote:
>> And still getting better here.
>>
>> I've reset some Seabios config.h options to defaults and disabled FLOPPY
>> options.
>
>The fl
On Sat, Jan 01, 2011 at 12:45:16AM -0500, Kevin O'Connor wrote:
>On Fri, Dec 31, 2010 at 04:02:09PM -0900, Roger wrote:
>> On Fri, Dec 31, 2010 at 11:37:52AM -0500, Kevin O'Connor wrote:
>> >On Fri, Dec 31, 2010 at 01:54:04AM -0900, Roger wrote:
>>
s.
A good easy example would be setting DRAMC:
DRAMC, 0x00, 0x08,
Is the "0x00" designated by "000" as documented? Hex?
What does "0x08" mean?
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On Mon, Jan 03, 2011 at 12:14:39AM -0500, Corey Osgood wrote:
>On Sun, Jan 2, 2011 at 8:03 PM, Roger wrote:
>> I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a
>> little mystified on setting the settings.
>>
>> I can see where settings a
that
>programming done. You'll just want to make sure the board (and RAM)
>can run properly under coreboot, but I don't need to see any dumps
>from it for now.
I'll check into this sometime soon.
--
Roger
http://rogerx.freeshell.org/
00:00.0 Host bridge: Intel Corporation
t
>programming done. You'll just want to make sure the board (and RAM)
>can run properly under coreboot, but I don't need to see any dumps
>from it for now.
I'll check into this sometime soon.
--
Roger
http://rogerx.freeshell.org/
00:00.0 Host bridge: Intel Corporation 440
On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
> Hi
> Parts of original patch are already in coreboot. This version made cache
> work in my board now. It might need work so it doesn't break others. Here
> is part of serial capture. Rest is attached
Got the following on comp
On Sat, Jan 08, 2011 at 03:22:15AM +0100, Idwer Vollering wrote:
> 2011/1/8 Roger <[1]rogerx@gmail.com>
>
> On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
> > Hi
> > Parts of original patch are already in coreboot. This version made
make target
`/home/roger/src/coreboot-tyan/coreboot/build/config.h', needed by
`build/lib/uart8250.romstage.o'. Stop.
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On Sat, Jan 08, 2011 at 08:37:53PM +, Jouni Mettälä wrote:
> Updated patch with l2_cache.h added
> Signed-off-by: Jouni Mettälä <[1]jtmett...@gmail.com>
>
>References
>
> Visible links
> 1. mailto:jtmett...@gmail.com
OK. V3 compiled file. My previous uart missing file looks to be my f
within the code. Looks like somebody substituted commas for spaces on
some of the flags used.
Seems I've corrected some within both xcompile and abuild, but am still
getting "/bin/sh: -fno-stack-protector: command not found" some place.
Attaching an svn diff of what I have so
Here's several logs detailing differences between warm & cold boot raminit.
(With 4 slot SDRAM banks enabled within .config. using Tyan S1846 mainboard
layout.)
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I've applied the patch here and have been testing on a Tyan 1832DL using the
Tyan 1846 mainboard and am not seeing any of the patch's printk output within
the logs here.
I have grepped for L2 & rdmsr.
I can see where one of the patch files links in SLOT1 cpu with
the 67x cpu. Can also see where
s?
>Is this board in SVN already?
This is using the Tyan S1846 as a template for my Tyan S1832DL. The S1846 is a
single processor, mine is a dual processor.
However, it's probably getting to that point where I need to create a new
profile for the S1832DL.
>
>Thank
On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
>Hi all,
>
>Here is the new L2 cache patch. Sign-off in the patch itself. Still
>very juicy and tasty at 25k. :D
>
>Also done is including cpu/intel/model_68x again in slot_1. Otherwise
>it will die with a Coppermine P3 installed.
ug. I'm
.
FYI: Have 450P3 and 2x750P3's here and none of my coreboot logs state anything
about L2 being activated. From what you're saying, the L2 cache is entirely
automatically activated on Coppermines.
Cheers.
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On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
>Hi all,
>
>Here is the new L2 cache patch. Sign-off in the patch itself. Still
>very juicy and tasty at 25k. :D
>
>Also done is including cpu/intel/model_68x again in slot_1. Otherwise
>it will die with a Coppermine P3 installed.
>
>My boo
e P3 installed.
>
>My boot log on P2B-LS and a Katmai 600MHz attached.
>
>I have optimized it some more, and added more information and
>meaningful constants as I cross checked the code with Intel's
>documentation. Some debugging messages are different too. Give this a
>good
on on this porting.
roger
> 在 2014年7月3日，下午3:04，David Hendricks 写道：
>
> [+jiming@intel.com]
>
>
>
>> On Wed, Jul 2, 2014 at 5:58 PM, Paul Wilcox-Baker
>> wrote:
>> Dear coreboot,
>>
>> We have done some more research on the differences bet
er. Anybody compile coreboot for this
type of motherboard and if so what is the best approach ?
THanks,
/RS
--
====
Roger Sistla
sistla dot roger at gmail dot com
-Output from flashrom utility
Calibrating delay loop... OK.
No
Is there anywhere to get the sdk software other than cwlinux?
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