* Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]:
e820: BIOS-provided physical RAM map:
BIOS-e820: [mem 0x-0x0009fbff] usable
BIOS-e820: [mem 0x0009fc00-0x0009] reserved
BIOS-e820: [mem 0x000f-0x000f]
* Alexandru Gagniuc mr.nuke...@gmail.com [150214 02:14]:
It's that time of the year it seems. Last year, there were talks about
reducing the number of gerrit submitters. I'm certain you remember the anger
this caused amongst non-commercial members of the community when the proposed
list
* Alexandru Gagniuc mr.nuke...@gmail.com [150214 01:13]:
On Saturday, February 14, 2015 12:05:28 AM Marc Jones wrote:
Hi Everyone,
Hi,
Please update the wiki page with project ideas.
http://www.coreboot.org/Project_Ideas
That's the first unlocked page in the coreboot wiki I have
* Kuzmichev Viktor kuzmichevvikt...@gmail.com [150120 14:31]:
Hello,
I'm trying to load Memtest86+ on the Mohon Peak reference board from
CBFS and it fails.
My primary payload is SeaBIOS. Memtest is added using cbfstool, so
the layout of my ROM file is as follows:
$ ./build/cbfstool
* Fred Young fred.yo...@kaleidescape.com [150107 16:46]:
The last time that I synched my coreboot source was about 2 weeks ago. I just
tried the latest FSP and I still have the same problem. When I load Linux, I
do
see video output.
Your video bios executes, and fails because an int15
Dear coreboot community members:
Marc, Ron, Patrick, Aaron and I have been discussing for a while about how
to make coreboot more accessible for businesses. We would like to found a
business organization (a.k.a. a coreboot consortium) that helps commercial
players out there to become a part of
* Bucsi Andor andor.bu...@outlook.com [141203 19:52]:
/home/harish/opensource/coreboot/payloads/coreinfo/util/kconfig/lxdialog/
dialog.h:22:19: fatal error: fcntl.h: No such file or directory
Did you install libc6-dev?
Stefan
--
coreboot mailing list: coreboot@coreboot.org
On 11/21/14 4:31 AM, Idwer Vollering wrote:
2014-11-21 6:03 GMT+01:00 The Gluglug i...@gluglug.org.uk:
One possible solution is to simply upgrade GCC, which I will, but I
would also like to get cbfstool to build again for this version of
GCC. The patch in the gerrit link works, but is not
On 11/20/14 9:40 PM, Scott Duplichan wrote:
The Gluglug [mailto:i...@gluglug.org.uk] wrote:
]-BEGIN PGP SIGNED MESSAGE-
]Hash: SHA1
]
]Hi,
]
]cbfs-mkstage.c: In function ‘is_phdr_ignored’:
]cbfs-mkstage.c:45:84: error: cast to pointer from integer of different
]size
On 11/19/14 11:36 AM, Gailu Singh wrote:
Hi Experts,
I am using Baytrail SoC board (Bayleybay CRB) and testing
suspend/resume from Linux (kernel 3.10). I can suspend with pm-suspend
and resume with power button; however after resuming I get following
logs in Linux
Corrupted low memory at
* Gailu Singh gail...@gmail.com [141119 20:36]:
Hi Experts,
I am using Baytrail SoC board (Bayleybay CRB) and testing suspend/resume from
Linux (kernel 3.10). I can suspend with pm-suspend and resume with power
button; however after resuming I get following logs in Linux
Corrupted low
* ron minnich rminn...@gmail.com [14 23:23]:
I have a friend who has a parallel port programmer for a 2764. He needs to
program it.
Options?
1. Get a pin-compatible replacement for a 2764
Any 27C64 should work.
2.get a USB to parallel port adapter
As Felix said.
3. get something
Hi,
while this was addressed at AMD, I feel compelled to add my 2ct to some
of this.
* Peter Stuge pe...@stuge.se [141106 16:07]:
As these contributions started to flow into the community many years
ago, you may remember that I guessed that such rules would exist and
asked *literally* what
* ron minnich rminn...@gmail.com [140827 18:43]:
I need to set up qemu with a 64MiB ROM.
I figure supporting EFI has made QEMU capable of such things, but if
anyone has direct experience with this, please let me know. I tried it
a few years back (2008) and it did not work at all ... I guess
* Peter Stuge pe...@stuge.se [140814 23:31]:
Isaac wrote:
The new nvidia/tegra124 support requires a build tool from NVIDIA called
cbootimage (https://github.com/NVIDIA/cbootimage). I'm not sure of the best
way to add support into coreboot so I'd like to get some feedback.
I would
* ron minnich rminn...@gmail.com [140809 05:24]:
Some of furquan's very fine work from -- yegads! -- a year ago is just
now coming upstream. Take a look.
Ron! If you have a link for us, that would be great!
I want to endorse Furquan's great work, however. Not only did it open up
new ways of
* Gregg Levine gregg.drw...@gmail.com [140805 21:35]:
Hello!
Stefan, by what you posted there, (and correct me if I'm wrong) if I
were to put together a system who would be running ChromeOS and of
course using coreboot to bring it up, the OS would be constructed from
the head of the entire
* Paul Menzel paulepan...@users.sourceforge.net [140802 15:07]:
As already commented on your change sets, I’d prefer if you could avoid
squashing commits. Kyösti made very good points, so I won’t repeat them.
One of the reasons Isaac has been squashing patches was that some in the
community
* Kyösti Mälkki kyosti.mal...@gmail.com [140731 21:00]:
Do you plan to upstream all Chromebook coreboot and libpayload
branches from Chromium git, or just the individual patches Sage
finds useful and necessary for the boards You currently work on?
No, the plan for now is to only upstream the
* Patrick Georgi patr...@georgi-clan.de [140805 21:32]:
Am 05.08.2014 um 20:36 schrieb Stefan Reinauer:
Are you suggesting that the needs have changed here?
My only concern here would be to keep rebase/merge et al more
functional, but it's probably already too late
* Stefan Berger stef...@linux.vnet.ibm.com [140714 12:14]:
The TPM is successfully detected but sending TPM_Startup(ST_Clear)
to the TPM fails since either coreboot or some other firmware seems
to already have initialized the TPM, which is fine, and also
extended PCR 0 with at least one hash.
Hi Richard,
* Richard A. Smith rich...@laptop.org [140710 19:45]:
http://ctl.net/education-chromebook/
Anyone know if these run coreboot and how locked down they are?
All new Chrome OS devices run coreboot and depthcharge, a payload that
implements a verified boot process. Chrome OS devices
* ron minnich rminn...@gmail.com [140514 19:22]:
what's an EFI OS?
An OS that implements the UEFI standard, e.g. TianoCore / edk2 ;)
This is under the assumption that every advanced boot loader eventually
turns into an operating system.
SCNR.
Stefan
--
coreboot mailing list:
* Vitor Augusto vitora...@gmail.com [140412 03:04]:
Hello.
I'm searching for any information about where (memory, IO port, etc.)
the status (on or off) of the fans of a laptop are stored. Anything is
very welcome! This is to improve the compatibility of i8kutils package
at Linux. The site
* Zoran s s_zo...@yahoo.com [140326 08:17]:
Hello Ron, Marc (Jones),
I am wondering where IOAPIC code resides (somewhere on SouthBridge) for IVB?
Could you (or anybody) point to me the file where this code exists/lives, so I
can inspect it and learn more about IOAPIC itself? This one is
* Andrew Wu andrewwu...@gmail.com [140327 14:00]:
Sorry, I checked Vortex86EX CPU datasheet, but it seems there is no
workaround can do it.
So if I want to get rid of romcc, maybe I have to write DRAM init code
in assembly, That is not very easy. :(
Don't worry we'll figure something out
* David Hendricks dhend...@google.com [140326 20:25]:
On Wed, Mar 26, 2014 at 9:47 AM, ron minnich rminn...@gmail.com wrote:
I think it's good and well written. I'd replace your 'panic levels' with 4
simple classifications and leave it at that.
Yep, good write-up overall.
I
* ron minnich rminn...@gmail.com [140325 06:34]:
On Mon, Mar 24, 2014 at 10:20 PM, Vladimir ' -coder/phcoder' Serbinenko
phco...@gmail.com wrote:
I don't see how this prevents any of my propositions for the bulk of the
boards. The problem you describe isn't going away with
* mrnuke mr.nuke...@gmail.com [140325 05:10]:
* For example, a hardwired boot blob which has been RE'd so that we know
what
it does and how it does it, would be acceptable (see Allwinner). Even the
FSF,
according to RMS's own essays considers this to essentially be hardware.
* A
* mrnuke mr.nuke...@gmail.com [140325 08:37]:
a branch containing that hash is not available publicly.
Baloney. Your not finding it does not mean it's not available. It means you
didn't look hard enough.
I call baloney on this one. I do not have to look hard enough. Section 3
* mrnuke mr.nuke...@gmail.com [140325 19:13]:
On Tuesday, March 25, 2014 06:56:13 PM Stefan Reinauer wrote:
* ron minnich rminn...@gmail.com [140325 06:34]:
On Mon, Mar 24, 2014 at 10:20 PM, Vladimir ' -coder/phcoder' Serbinenko
phco...@gmail.com wrote:
I don't see how
]:
On Thursday, March 20, 2014 10:55:57 PM Stefan Reinauer wrote:
* Build a MAINTAINERS file for common code, and encourage people to keep
subsystem maintainers in the loop for changes
[...]
This is somewhat what linux does, and it works well for them.
When we (Ron, Marc, Patrick, Peter
Hi Carl-Daniel,
thank you for your feedback!
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [140321 01:39]:
I see a huge bottleneck in restricting the number of committers to six.
- Corporate committers will be primarily obliged to get the stuff of
their own employer committed,
* Paul Menzel paulepan...@users.sourceforge.net [140325 00:20]:
Additionally I heard claims, that the GPLv2 license is violated as it is
currently impossible to rebuild the exact same image that is shipped
with the devices as it is not even clear what commit was used to build
the image and to
* David Hubbard david.c.hubbard+coreb...@gmail.com [140323 10:56]:
Coreboot can be relevant even if it only supports obsolete silicon. Coreboot
was the first to bring sub-second boot times to laptops. There are more
examples.
Yes, we worked hard to get to that goal. If it were about obsolete
* David Hubbard david.c.hubbard+coreb...@gmail.com [140323 20:33]:
On Sun, Mar 23, 2014 at 12:58 PM, Vladimir ' -coder/phcoder' Serbinenko
phco...@gmail.com wrote:
On 23.03.2014 19:24, ron minnich wrote:
So I believe the problem is not the idea of gatekeepers, but the
manner
* Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com [140321 04:31]:
The proposition of gatekeepers would essentially kill community effort.
Even in current infrastructure reviewing is a major slowdown. With small
number of gatekeepers there wouldn't be any significant contributions as
* Kyösti Mälkki kyosti.mal...@gmail.com [140322 18:44]:
Some changes to review process are certainly welcome. I just hope
Stefan would have included separate section of the current problems
and more details of the goals his proposal tries to address. Even
some of the obvious ones are not
* Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com [140321 04:13]:
The boards and chipsets are sufficiently well insulated from each other
so that it's possible to improve one without breaking the others. With
board-status the potential users and devs have a good overview which
* mrnuke mr.nuke...@gmail.com [140320 23:57]:
Proposal:
* Share these drivers between coreboot and libpayload.
* libpayload is BSD. Have a [ ] Enable GPL features config option which
unlocks the GPL'd drivers from coreboot.
* libpayload core remains BSD.
* coreboot drivers are
* Patrick Georgi patr...@georgi-clan.de [140321 18:38]:
Am Donnerstag, den 20.03.2014, 17:57 -0500 schrieb mrnuke:
* Share these drivers between coreboot and libpayload.
Make them BSD-l, like cbfs-core.
* libpayload core remains BSD.
with strings attached - I'd like to avoid that.
Nice
* Shant Kehyeian skehye...@gmail.com [140320 12:12]:
Hello,
I have Samsung ARM chromebook series 3 Snow and I am trying to flesh it and
change the boot process.
So I build a coreboot.rom for that, but before I start to do that I would like
to ask about the payload. When I did the make
coreboot for the 21st century
setting up the project for the next decade
Purpose: Purge all boards / chipsets / cpus that require ROMCC in
romstage and known broken chipsets (sc520, i855)
coreboot is now officially 15 years old. One and a half long decades
with ups and downs. During this time
consistency, scalability and conformity with the general
coreboot strategy, we need to define a clear committer structure that
defines the original project structure of having a benevolent dictator
aka project leader (Stefan Reinauer) and gatekeepers in place. The
suggested structure will need
* ron minnich rminn...@gmail.com [140320 22:37]:
I like this, I just wish we could remove more boards :-)
I was surprised that the number of boards still using ROMCC for romstage
was so low. We could also remove the revF and Fam10 boards because the
use non-standardized cache as ram
* Stefan Tauner stefan.tau...@student.tuwien.ac.at [140321 01:42]:
On Thu, 20 Mar 2014 22:33:21 +0100
Stefan Reinauer stefan.reina...@coreboot.org wrote:
dmp/vortex86ex
What's exactly wrong with that one? DMP ported their SoC themselves
less than half a year ago, and I seriously doubt
On Mar 15, 2014, at 10:22, Kevin O'Connor ke...@koconnor.net wrote:
On Wed, Mar 12, 2014 at 09:12:05PM +0100, Stefan Reinauer wrote:
* Peter Stuge pe...@stuge.se [140312 19:08]:
ron minnich wrote:
For the base identity map on x86-32, it's one page for 4G.
For a map which locks out page 0
* Peter Stuge pe...@stuge.se [140312 19:08]:
ron minnich wrote:
[on arm]
Why is it helpful or neccessary there?
It only matters if you like to have a dcache. Do you want a dcache?
What are the numbers?
Of running with dcache vs without? Beyond 10x speed improvement iirc.
Far too
* ron minnich rminn...@gmail.com [140310 22:43]:
Now you've just made me sad.
OK, given that in the beginning times we never supplied this little tidbit,
who
or what needs it? It looks like another memory turd whose time has gone.
ron
It's needed by some option roms. See void
* ron minnich rminn...@gmail.com [140310 23:24]:
Which option ROMs? newish ones or 3c509 :-)? Ah well guess I believe you. I
guess I never needed it because in my main uses we did not use or want option
roms -- we loaded Linux and there was no need there. Running some option rom
in
an 8086
* John Lewis jle...@johnlewis.ie [140129 23:16]:
Okay, well I extracted the attached file using:
eval `./fmap_decode bios.bin | grep BOOT_STUB`
dd if=c720.rom ibs=$((area_offset)) skip=1 | dd bs=$((area_size))
iflag=fullblock of=c720-coreboot.bin
You should use cbfstool on the whole 8MB
* Mono m...@posteo.de [140124 23:20]:
Hallo,
Would you help me on a coreboot port? I just installed coreboot on a Thinkpad
X60 following the wiki. Now I want it on this mid-2007 macbook2,1 too.
I read some pages in the wiki and started to collect information about the
macbook. it seems it
* Kyösti Mälkki kyosti.mal...@gmail.com [131213 11:29]:
Yet we have had commit 032c23db for 5 months:
intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write
Hi Alex,
thanks for this effort. Without having looked at the patches yet, I
think moving microcode into 3rdparty / blobs.git is the right way to
go. This is one of the (my) original intentions of having CBFS to begin
with.
Stefan
* mrnuke mr.nuke...@gmail.com [131214 00:48]:
Hi all,
* Kyösti Mälkki kyosti.mal...@gmail.com [131212 16:02]:
Hi
After commit 872c922 there is some trouble on PCI configuration
access with Asus M4A785-M. This could apply to other amdfam10 too,
although I have not yet received such reports.
As the commit message stated, I had discovered that
* Bradley M. Kuhn bk...@sfconservancy.org [131120 17:09]:
TL;DR: Coreboot applied to the Conservancy and has been offered
membership. The FSA template should be reviewed by all interested
parties, and we need your help to draft three specific sections,
which are discussed
* Denis 'GNUtoo' Carikli gnu...@no-log.org [131109 00:19]:
On qemu, coreboot is not necessary: some coreboot payloads (like
seabios) are capable of beeing the full bootstrap firware(because
qemu is really simple: most of the complex hardware already works).
Then I really wonder what's left
* ron minnich rminn...@gmail.com [131107 16:09]:
Very interesting note. We've never seen this before. Comments?
We did see this before.. We actually had a wbinvd there for a while, at
least in the ChromeOS tree. And removed it because it broke some
hardware.
Stefan
--
coreboot mailing list:
* Aaron Durbin adur...@chromium.org [131105 18:00]:
On Tue, Nov 5, 2013 at 10:55 AM, Kyösti Mälkki kyosti.mal...@gmail.com
wrote:
Hi
A recent discussion I had about google/stout suggested that with the sources
from coreboot git, this board is unable to resume from S3 suspend.
On 7/29/13 11:43 PM, Eugen Leitl wrote:
On Tue, Jul 30, 2013 at 02:40:16AM +0200, Stefan Reinauer wrote:
I agree with Alex: If you are concerned by this issue, please make an
effort to fix it. It would be great to bring the clear level of
separation that we have on newer systems to older CPU
* Aaron Durbin adur...@chromium.org [130724 17:16]:
A couple things to change:
CONFIG_CPU_ADDR_BITS=36
CONFIG_SPI_FLASH_NO_FAST_READ=y
I *don't* think this is causing you grief, but these are different
from the chromium repo.
Also, you .config shows a 4MiB cbfs, but that doesn't jive
* Kyösti Mälkki kyosti.mal...@gmail.com [130729 17:22]:
Did someone change the SPD eeprom address notation in pei_data from
7-bit to 8-bit addresses?
samsung/lumpy/romstage.c :
.spd_addresses = { 0x50, 0x00,0xf0,0x00 },
google/stout/romstage.c :
spd_addresses: { 0xA0,
* Alex G. mr.nuke...@gmail.com [130725 22:23]:
Denis,
We have in place a pretty darn good infrastructure of separating the
microcode from the coreboot stages. It's very easy to store microcode as
a _separate_ CBFS file. Not all CPUs use this, but changing this is
trivial. Patches welcome.
* tim zander t.zan...@uea.ac.uk [130611 16:02]:
Could we convince you to organize it on a coreboot.org/Chromebook
wiki page?
Sure, if you give me an account...
Done.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Tim Zander t.zan...@uea.ac.uk [130611 00:49]:
These 3 used Insyde H2C. They were all Atom based.
December 2010 Google Cr-48 Mario
support unknown/no
June 2011 Samsung Series 5 Chromebook Alex
support unknown/no
July 2011 AcerAC700
* Tim Zander t.zan...@uea.ac.uk [130611 02:50]:
Hardware Preparation
Open the case
You'll now have to disassemble your device (which most
likely voids your warranty).
Disable write protect
You'll have to locate the Write Protect jumper and enable it.
This
* Aaron Durbin adur...@chromium.org [130509 00:02]:
Am Mittwoch, den 08.05.2013, 08:18 -0500 schrieb Aaron Durbin:
The reason udelay was put in northbridge was for SMM if I am not
mistaken. How similar are the implementations?
Of `udelay.c`? Besides the register differences it is the
* Marc Jones marcj...@gmail.com [130502 17:15]:
Hi Aaron,
On Thu, May 2, 2013 at 8:32 AM, Aaron Durbin adur...@chromium.org wrote:
Hi folks,
I am wondering why the ramstage stack size is so large on a lot of boards:
$ grep -A 3 -r STACK_SIZE src/* | grep Kconfig | grep default | awk
* Aaron Durbin adur...@google.com [130502 17:39]:
OK. Thanks for the info. That does make for some huge memory
footprints on the AMD machines with a large number of CONFIG_MAX_CPUS.
I'd be curious to know why the BSP for the AMD code requires so much
while in ramstage.
-Aaron
One of the
* Patrick Georgi patr...@georgi-clan.de [130502 17:40]:
Am 02.05.2013 16:32, schrieb Aaron Durbin:
I am wondering why the ramstage stack size is so large on a lot of boards:
Is this just an artifact of copy-n-paste? What is driving the
requirement for such large stack sizes?
Other than
* Marc Jones marcj...@gmail.com [130502 20:24]:
On Thu, May 2, 2013 at 12:22 PM, Stefan Reinauer
stefan.reina...@coreboot.org wrote:
* Aaron Durbin adur...@google.com [130502 17:39]:
OK. Thanks for the info. That does make for some huge memory
footprints on the AMD machines with a large
* Kevin O'Connor ke...@koconnor.net [130430 03:21]:
On Sat, Mar 23, 2013 at 07:24:03PM +0100, Stefan Reinauer wrote:
I was thinking about completely disabling the trac based tracker for
coreboot completely since we are basically not using it anymore.
If you are looking for opinions, I'd
* Paul Menzel paulepan...@users.sourceforge.net [130422 17:04]:
could you please test building coreboot for your hardware with GCC 4.7.3
and report back your results [1]? Make sure to save your build with GCC
4.7.2 for comparison beforehand as `make crossgcc` will delete `build/`.
Did you mean
* Paul Menzel paulepan...@users.sourceforge.net [130409 00:51]:
Dear coreboot folks,
if somebody is bored ;-), here is the output of Cppcheck for cbfstool to
fix. :P
Since you already started looking into the issue, maybe you can save the
rest of us some time by following through with it
* CTO of SPCTNC spc...@gmail.com [130410 07:31]:
Please help me.
- How can I fix the problem.
It sounds like you have a RAM init problem (e.g. your RAM is not
working) because the chipset (945GC) is slightly different than
the other 945 variations that we have supported (just a guess)
-
* Pradish M P, ERS, HCLTech pradis...@hcl.com [130409 10:00]:
Dear Coreboot Folks
I see that this issues is still not resolved, can you guys give me some steps
so that I can do those changes in my local copy
And build libpayload.
Regards
Pradish
Please take a look at
Hi Paul,
* Paul Menzel paulepan...@users.sourceforge.net [130407 02:30]:
In #coreboot on irc.freenode.net, phcoder wrote the following.
• possible LZMA bug trigger is that GRUB uses 2 chunks
• I suppose that some variables aren't reset properly between chunks
Thanks for this analysis.
* Paul Menzel paulepan...@users.sourceforge.net [130402 12:16]:
Dear coreboot folks,
for example the patch adding the spkmodem console [1] is currently not
build tested as it is disabled by default.
Could we put a `.config.jenkins` file into the repository where more
stuff is enabled so
It looks like grub returns from execution. Probably because it's unhappy about
something ..
Were you able to use the same payload, say, in qemu?
On Apr 5, 2013, at 16:42, Paul Menzel paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
on the ASRock E350M1 I build coreboot
* Stefan Tauner stefan.tau...@student.tuwien.ac.at [130402 16:50]:
Hi,
please make Patrick and me (or at least him :) a (coreboot) wiki admin
so that we can delete obsolete pages, thanks.
Hi Stefan!
done.
Stefan, too.
--
coreboot mailing list: coreboot@coreboot.org
* Patrick Georgi patr...@georgi-clan.de [130403 13:47]:
Am 02.04.2013 12:11, schrieb Paul Menzel:
if I am not mistaken, all programs under `utils/` are currently not
built tested. Could that be changed, please? Maybe the following script
could be integrated somehow?
$ for s in
* Kevin O'Connor ke...@koconnor.net [130323 18:21]:
I definitely appreciate this change. Thanks!
I think moving the automated coreboot tracker s...@coreboot.org
emails off the list would be an improvement as well. :-)
-Kevin
Thanks for you mail, Kevin!
I was thinking about completely
Dear coreboot community,
it has been quite a while since we switched our version control system
to git + gerrit, and the incredible amount of emails has alienated one
or another person on this list, unfortunately. But help is finally here:
We switched all gerrit based email traffic over to a new
* Patrick Georgi patr...@georgi-clan.de [130320 11:52]:
Am 20.03.2013 11:28, schrieb Paul Menzel:
1. Is that even possible for AMD/ATI hardware in their current design
with ATOM BIOS and firmware?
For simply initializing the chip, tracing what the driver does works
just as well as on Intel
* Paul Menzel paulepan...@users.sourceforge.net [130320 10:13]:
Dear Stefan,
Am Mittwoch, den 20.03.2013, 09:22 +0100 schrieb Stefan Reinauer:
it has been quite a while since we switched our version control system
to git + gerrit, and the incredible amount of emails has alienated one
* Peter Stuge pe...@stuge.se [130320 23:15]:
Stefan Reinauer wrote:
bringing an issues to broader attention or discussion. On what
list should that happen?
I think that everybody can make a judgement call on how they would
like to implement stuff like that for themselfes.
I'd
in the
community while maintaining a high quality code base.
--
Stefan Reinauer
Google Inc.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Jens Rottmann jrottm...@lippertembedded.de [130306 17:29]:
Hi Martin (and all),
I wrote:
You dereference dev in line 132, so if it's really 0,
will you then ever reach this check?? (I don't know if
in romstage *NULL is caught.)
You wrote:
yes, if it's 0, we still reach the code.
* Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com [130121 15:10]:
A new version of spkmodem. This one doesn't lose the bit sync even if I
disconnect the cable for the short time (but, of course data sent when
no cable is attached is lost)
--
Regards
Vladimir 'φ-coder/phcoder'
* Philip Schulz p...@phisch.org [121211 14:17]:
Hi,
I'm not subscribed, so please cc: me if you want me to see your email.
Peter Stuge wrote:
David Hendricks wrote:
http://www.phisch.org/website/efiboot/
Hi Philip,
die Seite scheint nicht mehr verfuegbar zu sein, hast Du sie
* Stefan Reinauer stefan.reina...@coreboot.org [130115 01:25]:
* Philip Schulz p...@phisch.org [121211 14:17]:
Hi,
I'm not subscribed, so please cc: me if you want me to see your email.
Peter Stuge wrote:
David Hendricks wrote:
http://www.phisch.org/website/efiboot/
Hi Philip
* Rudolf Marek r.ma...@assembler.cz [121105 23:02]:
Hi
Anyone knows what happen to my attachment?
Trying second time, first time it was also included...
Thanks
Rudolf
Weird... there does not seem to be an attachment, either time.
Can you upload the patch to gerrit instead?
Stefan
* Peter Stuge pe...@stuge.se [121025 23:07]:
Hi,
A Shirwaikar, Atita wrote:
In Qemu environment and using coreboot, we are trying to install
Windows 7 on our virtual disk. Installation fails throwing this error.
Windows failed to load because the firmware (BIOS) is not ACPI
Hi Chris,
some people on this mailing list had success with their ChromeBooks. I
don't know if anyone in the community tried the ChromeBox yet, but it
should be fairly similar.
You will need an external flash writer, and/or disable the machine's
hardware write protection for the SPI flash (the
* Wang, SiYuan siyuan.w...@amd.com [120904 07:33]:
Hi,
there is problem when I use git commit to commit changes. the message says:
test failed:
'build/.../static.c build/.../static.c build/.../static.ramstage.o
build/.../static.romstage.o' should be 'build/.../static.c build/.../static.c
* Stefan Tauner stefan.tau...@student.tuwien.ac.at [120826 21:31]:
As you probably all know the procedure to relieve the coreboot-
supported thinkpads from their proprietary firmware is not completely
trivial[1]. The main problem is that the vendor has locked down the
available SPI opcodes
* ron minnich rminn...@gmail.com [120814 19:09]:
The plan, long ago, when it was still linuxbios, was that linux would
be the basis of interaction. Back then we were booting linux out of
flash faster than any known bios would put up a screen. We had tools
(rdcmos etc.) to manipulate cmos. We
On 6/9/12 6:43 AM, Kevin O'Connor wrote:
On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote:
I wonder if we need another option :-( to configure the rom but not run it?
Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but
CONFIG_VGA_ROM_RUN is not?
-Kevin
On 6/6/12 11:28 AM, Fengwei Zhang wrote:
Hi All,
My name is Fengwei. For one of my research project, I need a relative new
Coreboot supported board with SMM working. I am wondering if there is a list of
Coreboot supported boards with SMM working.
I have been working with board ASUS M2V-MX_SE,
On 5/12/12 1:43 AM, ali hagigat wrote:
If the CPU wb (write back) cache is enabled for the memory range,
ramstage() is OK. But CPU can not work with UC(uncached) memory type
in Coreboot code. If i define the whole memory un-cached right before
jumping to ramstage code ( cbfs_and_run()), CPU
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