* Peter Stuge pe...@stuge.se [110117 02:32]:
Kevin O'Connor wrote:
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Shouldn't cn700.c code be changed instead, so that it
sure to also teach the magic value to cbfstool (and possibly add a
magic value to some coreboot include file and use that instead) Those
file types are increasingly hard to keep track of.
Acked-by: Stefan Reinauer ste...@coreboot.org
Stefan
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* Patrick Georgi patrick.geo...@secunet.com [110114 15:40]:
Hi,
there are some strict aliasing related warnings in nvramtool.
This patch fixes them.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Nils njaco...@hetnet.nl [110114 17:36]:
Hi Stefan,
You wrote:
It doesn't occur with the coreboot toolchain iirc though
I did a fresh unmoddified checkout on r6255.
Then i did buildgcc.
The downloading/building of this beast takes more than an hour on my old
laptop. :)
Then i got the
* Myles Watson myle...@gmail.com [110110 14:29]:
On Mon, Jan 10, 2011 at 6:27 AM, Sven Schnelle sv...@stackframe.org wrote:
Myles Watson myle...@gmail.com writes:
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..d761cba 100644
---
* Nils njaco...@hetnet.nl [110114 23:44]:
OK i spent the whole evening experimenting with crossgcc again but i don't
get
it running.
How can i check if the crosscompiler is used?
cat .xcompile
That doesn't find anything when executed in my topmost coreboot directory.
This is
-by: Stefan Reinauer ste...@coreboot.org
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.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Peter Stuge pe...@stuge.se [110114 02:35]:
Nils wrote:
I did a abuild run on r6252 and got the following error:
Building technologic/ts5300; i386: ok
Creating config file... ok; Compiling image on 1 cpu .. FAILED after 19s!
Log excerpt:
/bin/sh: -Wa,--divide: not found
These include files are unused, they are never included
src/cpu/amd/model_10xxx/mc_patch_0120.h
src/cpu/amd/model_10xxx/mc_patch_0183.h
src/cpu/amd/model_10xxx/mc_patch_0184.h
src/cpu/intel/model_f1x/multiplier.h
src/cpu/intel/model_f0x/multiplier.h
src/southbridge/amd/cs5536/smbus2.h
* Scott Duplichan sc...@notabs.org [110112 23:35]:
On Wed, Jan 12, 2011 at 12:39 PM, Stefan Reinauer ste...@coreboot.org wrote:
These include files are unused, they are never included
src/cpu/amd/model_10xxx/mc_patch_0120.h
src/cpu/amd/model_10xxx/mc_patch_0183.h
src/cpu/amd
* Ward Vandewege w...@gnu.org [110112 23:12]:
Hi all,
If one enables expert mode in Kconfig and builds a fam10 board, this is what
happens:
$ make clean make
ROMCC mainboard/supermicro/h8qme_fam10/bootblock.inc
GENbootblock/bootblock.S
CC
* Joseph Smith j...@settoplinux.org [110113 01:00]:
Hello,
I am working on a new mainboard/northbridge and have got it all the
way to Jumping to image and then it immediately restarts and loops
at that point over and over. I even did a ram_check() on the whole
memory (accept vga range) and it
* Peter Stuge pe...@stuge.se [110110 21:34]:
Nice, a ThinkPad patch! :) Many have wanted that.
Sven Schnelle wrote:
commit 7d3a1ebf3de5746d3dec8f47e74458c15018c694
Author: Sven Schnelle sv...@stackframe.org
Date: Mon Jan 10 13:23:59 2011 +0100
Initial bits for X60 support
* Marc Bertens mbert...@xs4all.nl [110107 12:11]:
-Original Message-
From: Stefan Reinauer ste...@coreboot.org
To: coreboot@coreboot.org
Subject: Re: [coreboot] [commit] r6247 - trunk/src/mainboard/nokia/ip530
Date: Fri, 7 Jan 2011 01:21:26 +0100
This is not particularly
This is not particularly beautiful. Is there any advantage of using the
irq hack rather than putting this as code into some mainboard specific
init function?
@@ -40,10 +40,55 @@
+ device pnp 3f0.8 on# AUX I/O
+irq 0x24 = 0x84 # OSC
+
+
* Bao, Zheng zheng@amd.com [110105 10:14]:
Fix some settings of AMD MCT. It is based on BIOS test suite.
Signed-off-by: zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
Stefan
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* Peter Stuge pe...@stuge.se [110104 12:21]:
She, Kerry wrote:
Thanks! I think this is a nice addition. Maybe we should add a
Kconfig option to choose between cimx and non-cimx?
I think we should, once we actually hit a use case.
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* Peter Stuge pe...@stuge.se [110104 22:18]:
Stefan Reinauer wrote:
Maybe we should add a Kconfig option to choose between cimx and
non-cimx?
I think we should, once we actually hit a use case.
Um? This is the case right here.
Oh? Which board? I thought the patch said for reference
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [110105 00:05]:
Still, having the code checked in is IMHO better than having it on the
list. If there are any CIMx integration issues later, we still have the
alternative code (and as a nice benefit, we can actually touch that code
On 1/2/11 10:00 AM, ali hagigat wrote:
Coreboot declares a complete documentation of some chips by:
http://www.coreboot.org/Datasheets
and particularly 82815E by:
http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29
Where is the documentation for integrated graphics controller
Hi Keith,
On 1/2/11 3:59 AM, Keith Hui wrote:
I also want to get the SCSI part of my P2B-LS
fully working. This also means implementing an option table for this
board.
Why would that be required?
I am looking for pointers on what to read to know the relationships
between option tables,
On 31.12.2010, at 10:50, Roger rogerx@gmail.com wrote:
Also should make mention, the following command not found and I do
have /bin/sh - /bin/bash here.
CC cpu/intel/microcode/microcode.ramstage.o
CC cpu/x86/name/name.ramstage.o
AR coreboot.a
CC
On 31.12.2010, at 10:07, Roger rogerx@gmail.com wrote:
1) If I use coreboot's Run VGA Option ROMs, I can get VGA up and the first
thing displayed is one text line of something like SeaBIOS Version
And then I usually get some of my other PCI devices option roms executing as
well on
On 12/30/10 3:26 AM, Bao, Zheng wrote:
Add RS785(RS880) support. Just few pci_ids.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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On 12/30/10 4:27 AM, Bao, Zheng wrote:
Add detection of Nuvoton WPCM450.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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On 12/30/10 5:03 AM, She, Kerry wrote:
add amd bimini mainboard support
Signed-off-by: Kerry She kerry@amd.com
Great work!
Acked-by: Stefan Reinauer ste...@coreboot.org
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On 12/30/10 5:03 AM, She, Kerry wrote:
sb800 southbridge CIMx code
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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On 12/30/10 5:04 AM, She, Kerry wrote:
add amd sb800 southbridge support
Signed-off-by: Kerry She kerry@amd.com
Dear Kerry,
thanks a lot for making this possible.
Regards,
Stefan
Acked-by: Stefan Reinauer ste...@coreboot.org
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On 12/29/10 4:51 PM, Saku Sammakko wrote:
Hello
Will coreboot work with the following hardware?
Acer Travelmate 8100
main board (dmidecode): Acer Kingfisher
cpu: Intel M 730 1,6GHz, 533MHz fsb, 2MB L2 cache
northbridge (lspci): Intel Corporation Mobile 915GM/PM/GMS/910GML
Express
the issue.
Stefan
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Index: util/superiotool/ite.c
===
--- util/superiotool/ite.c (revision 6219)
+++ util/superiotool/ite.c (working copy)
@@ -798,6 +798,8 @@
regwrite(port
On 12/30/10 12:13 PM, Stefan Reinauer wrote:
On 12/28/10 11:51 PM, David Hendricks wrote:
On Tue, Dec 28, 2010 at 4:13 AM, Frantisek Rysanek
frantisek.rysa...@post.cz mailto:frantisek.rysa...@post.cz wrote:
Dear maintainers of the superiotool,
I have the following feature request
* Kevin O'Connor ke...@koconnor.net [101228 01:00]:
CONFIG_AHCI is a bit experimental. Has there been success with it on
real hardware?
I have not tried it. It sounded like a great idea though.
+checkout:
+ test -d seabios ( cd seabios; git pull ) || \
+ git clone
On 12/30/10 10:48 PM, Nils wrote:
- {0x,{0x, 0x}},
+ {0x,{0x, 0x}},
I don't think we should capitalize hexadecimal numbers. We never did (on
purpose) anywhere else.
Bikeshed, anyone?
On 12/27/10 7:45 PM, Marc Bertens wrote:
Signed-off: Marc Bertens mbert...@xs4all.nl mailto:mbert...@xs4all.nl
There was a problem when using the getpir utility with the
coreboot_ram file, basically removed the loop around the search
function, in the coreboot_ram image the start $PIR is not
On 26.12.2010, at 06:19, Peter Stuge pe...@stuge.se wrote:
Nils wrote:
-__asm__ __volatile__(hlt\n);
+while(1) {
+__asm__ __volatile__(hlt\n);
+}
Why not call die() instead? Is it too early for that?
Die() is now extra. It should work early.
--
On 12/26/10 3:12 PM, repository service wrote:
Modified: trunk/src/drivers/dec/21143/21143.c
==
--- trunk/src/drivers/dec/21143/21143.c Sun Dec 26 06:24:50 2010
(r6211)
+++
See patch
Today, if the user selects no payload at all, an image is created that
will leave the system bricked when flashed. This patch adds an easy way of
selecting SeaBIOS as a payload and makes it the default (instead of no
payload, which still exists as an option)
Signed-off-by: Stefan
On 12/21/10 8:04 PM, Russell Whitaker wrote:
On Wed, 22 Dec 2010, Stefan Reinauer wrote:
* Fengwei Zhang namedy...@gmail.com [101222 00:31]:
backup_resume copies some memory into a safe place because it will be
overwritten by copying coreboot to memory. After coreboot's device
allocation
* Fengwei Zhang namedy...@gmail.com [101222 00:31]:
Hi all,
I have tested S3 on board m2v-mx_se. it works. But if I put two DDR2
on board, it would die at post_cache_as_ram. it because stack
variable resume_backup_memory changed its value to 0x after
invoking
On 12/18/10 6:01 AM, Tadas S wrote:
I have inserted USB2.0 pci extension card to msi ms6119 mainboard.
The problems appear when I try to boot from USB flash drive attached
to that controller. If coreboot detects that controller as EHCI, the
boot fails just at FILO.
If coreboot detects it as
See patch
The same mechanisms are used for normal and fallback images.
Hence drop the FALLBACK_ prefix
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Index: src/Kconfig
===
--- src/Kconfig (revision 6203)
+++ src/Kconfig
Can we automatically determine the value of RAMTOP during build time?
On 17.12.2010, at 12:29, Patrick Georgi patr...@georgi-clan.de wrote:
Am Freitag, 17. Dezember 2010, um 15:08:38 schrieb Fengwei Zhang:
I would appreciate if someone could explain a little bit for me.
CONFIG_DCACHE_RAM_BASE
* Myles Watson myle...@gmail.com [101217 22:01]:
On Fri, Dec 17, 2010 at 1:50 PM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
Can we automatically determine the value of RAMTOP during build time?
Yes. It's a config variable. It's not the top of physical RAM, it's
the top
Hi Rudolf,
thanks for your comments... I will try to work them into the code.
But here is some more discussion, maybe I am still confused.
* Rudolf Marek r.ma...@assembler.cz [101214 23:54]:
Hi,
I will be back on the weekend. Just a comment to this:
+void smm_init(void)
+{
+msr_t
* Joseph Smith j...@settoplinux.org [101215 15:48]:
src/arch/x86/Makefile.inc contains code for MBI, which is (as far as I can
see)
specific to a single chipset. That simply doesn't belong in there, but so far
there is no other way to do it.
Oh no, the MBI code can work with all Intel
* Patrick Georgi patr...@georgi-clan.de [101215 17:18]:
As this is the default case on our platform, we already handle it that way.
filename-position is supposed to be the location in the target's address
space,
so if you want to store a file in the middle of a 1MB flash chip, you tell
* Joseph Smith j...@settoplinux.org [101215 17:20]:
On 12/15/2010 11:04 AM, Peter Stuge wrote:
Great idea in general.
Patrick Georgi wrote:
filename-position
This one is tricky. Blobs may need to have alignment, a negative
offset (ie. start at end of flash - $amount) rather than a
* Patrick Georgi patr...@georgi-clan.de [101215 12:51]:
Hi,
We have a couple of chipsets in the tree that require external data in CBFS,
sometimes with placement requirements (eg. for embedded controllers), and
there will be more of that kind to come.
Right now, we're adding Kconfig
On 15.12.2010, at 11:17, Xavi Drudis Ferran xdru...@tinet.cat wrote:
or are there going to be
parts of coreboot without source in the svn (so someone might be using
sourceless code
without knowing).
I think the idea is just to allow blobs being handled locally instead of in the
main
* Scott Duplichan sc...@notabs.org [101215 22:33]:
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Patrick Georgi
Sent: Wednesday, December 15, 2010 03:08 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH]Allow
Acked-by: Stefan Reinauer ste...@coreboot.org
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characters as per spec).
Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as product ID,
and truncate/fill it to 12 characters as per spec, if needed.
Abuild-tested.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Stefan Reinauer ste...@coreboot.org
Please remember to add
* xdrudis xdru...@tinet.cat [101216 01:53]:
I don't care where it runs. For me it's more whether it's been derived from
some other form and what's more useful to touch if you want to change it.
There's also the question of whether it can be replaced, but if it couldn't
it wouldn't be included,
On 12/15/10 1:05 AM, Uwe Hermann wrote:
However, please refrain from removing the verb adding code from those
boards that actually have sound jacks. It makes no sense to remove the
codecs and add the same code later on. Instead it should just be fixed
as soon as the right information is known
-11-11:
- integrated Rudolf's suggestions
- use normal IO PCI access (and backup 0xcf8 accordingly)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/via/vt8237r/vt8237r.h
===
--- src/southbridge/via/vt8237r
On 12/15/10 6:48 AM, Joseph Smith wrote:
Acked-by: Joseph Smith j...@settoplinux.org
And
Acked-by: Stefan Reinauer ste...@coreboot.org
Please go ahead and check in.
Index: coreboot-poulsbo/src/arch/x86/Makefile.bigbootblock.inc
* repository service s...@coreboot.org [101213 20:59]:
Modified: trunk/src/northbridge/intel/i945/raminit.c
==
--- trunk/src/northbridge/intel/i945/raminit.cMon Dec 13 20:53:58
2010(r6172)
+++
* repository service s...@coreboot.org [101213 20:50]:
Author: ruik
Date: Mon Dec 13 20:50:25 2010
New Revision: 6171
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6171
Log:
We hardcode highmemory size in every northbridge! This is bad, and
especially if suspend to ram is
Hi Tobias,
thanks a lot for your work. It's good to see people bringing new
features into more coreboot boards.
However, unfortunately, I have to put a big NACK on this one...
The below is very ugly, sorry to say. Please rework that code. I know
it's taken from the AMD cache as ram code, and
On 13.12.2010, at 03:10, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi,
The CF is the primary master and the IDE interface is the primare slave.
I've tried to enable the PATA MSR but lspci -vvv displays the IDE controller
as [disabled] (base at 1f0h and 170h in memory space). Is
On 13.12.2010, at 14:42, Tobias Diedrich ranma+coreb...@tdiedrich.de wrote:
BTW, via/epia-m700 defines HAVE_ACPI_TABLES, but does not supply a dsdt.asl
(only a get_dsdt script)
We should disable that and drop the script. Using foreign DSDTs might be
legally problematic..
Stefan
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and locking
- prevent copying SMM code multiple times
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Index: src/southbridge/via/vt8237r/vt8237r.h
===
--- src/southbridge/via/vt8237r/vt8237r.h (revision 6169)
+++ src
On 12/12/10 5:25 PM, Stefan Reinauer wrote:
See patch. This adds SMM support for Asus M2V-MX SE.
Please, test if you can!
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Hi,
I just added two new items to our upgrade guide for developers called
Flag Days:
http://www.coreboot.org/Flag_Days
However, it seems we neglected this practice for roughly 140 revisions
between r5911 and r6149. If you made any changes that will require
people update their uncommitted work,
On 12/11/10 12:57 PM, Peter Stuge wrote:
Uwe Hermann wrote:
Cleanup up HD audio codec / hda_verb.h files.
..
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Peter Stuge pe...@stuge.se
However, please refrain from removing the verb adding code from those
boards that actually have
Ooops that was intended for the list.
On 12/11/10 12:21 PM, Stefan Reinauer wrote:
On 12/11/10 3:49 AM, Uwe Hermann wrote:
The following files can be safely dropped as they don't match the ID
of the audio codec and thus will never get actually used (you'll see
HDA: no verb! or similar
,
Rudolf
Wow, nice finding. Assuming it's abuild tested and tested on real
hardware:
Acked-by: Stefan Reinauer ste...@coreboot.org
Stefan
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* Rudolf Marek r.ma...@assembler.cz [101212 01:10]:
Hi,
Yes it is tested on real HW. Attaching refreshed patch because
#if CONFIG_ ... SOCKET939 == 1
#endif
Is undefined, so I changed that to
#if defined()
that's not good enough i think. It might be 0, then defined would hit
* Peter Stuge pe...@stuge.se [101210 17:54]:
Patrick Georgi wrote:
Set the register based on the ROMSIZE.
..
How about
pci_write_config16(dev, 0x6c,
0x1-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)6));
instead?
I have a greater problem with this;
It assumes that one image will
* Scott Duplichan sc...@notabs.org [101210 18:13]:
Peter Stuge wrote:
]I have a greater problem with this;
]
]It assumes that one image will always go into one and the same size
]of flash chip.
I think I understand your concern. It is convenient to be able to
use a bigger chip to test
* Jonas Bülow jonas.bu...@gmail.com [101209 22:36]:
SerialICE sounds interesting. Is the project still alive?
Yes, it is. Alive and waiting for contributions. :-)
Stefan
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* David Robinson drobin...@bluechiptechnology.co.uk [101209 10:40]:
Hi,
The attached patch fixes a problem preventing Windows XP / 7 from booting with
bug check error A5 (0x0011, 0x0006) on the Gigabyte GA-M57SLI- S4
board. Microsoft documentation states that this bug check
On 08.12.2010, at 03:17, Patrick Georgi patr...@georgi-clan.de wrote:
Am 08.12.2010 07:20, schrieb Stefan Reinauer:
On 12/7/10 10:00 PM, Peter Stuge wrote:
repository service wrote:
first round name simplification. drop the component_ prefix.
Beautiful.
+++ trunk/src/mainboard/advantech
and are potentially reusable by
other chipsets, keeping them outside of amd/ dirs makes sense IMHO.
Alright
Acked-by: Stefan Reinauer ste...@coreboot.org
Uwe.
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http://randomprojects.org | http://unmaintained-free-software.org
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* repository service s...@coreboot.org [101208 22:40]:
Author: ranma
Date: Wed Dec 8 22:40:12 2010
New Revision: 6153
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6153
Log:
This patch instead dynamically generates the processor statement.
I can't use the speedstep
* repository service s...@coreboot.org [101208 22:40]:
Author: ranma
Date: Wed Dec 8 22:40:12 2010
New Revision: 6153
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6153
Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de
Acked-by: Peter Stuge pe...@stuge.se
Added:
* repository service s...@coreboot.org [101208 22:45]:
Author: ranma
Date: Wed Dec 8 22:45:57 2010
New Revision: 6154
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6154
Log:
These empty files sneaked in from another patch and shouldn't have been
included in r6153, remove
Hi Uwe,
good approach!
* Uwe Hermann u...@hermann-uwe.de [101206 23:45]:
Move select CACHE_AS_RAM lines from boards into CPU socket.
I generally like this idea, but that is not the only thing the patch
does. If it did, it were Acked-by: Stefan Reinauer ste...@coreboot.org
All K8/Fam10h
* Patrick Georgi patr...@georgi-clan.de [101207 16:35]:
Am 06.12.2010 23:45, schrieb Uwe Hermann:
See patch.
src/cpu/Kconfig defines CACHE_AS_RAM to !ROMCC, so I think these can
be dropped completely. Right?
We basically assume it's CAR unless romcc is used.
This seems to make a lot of
* Stefan Reinauer ste...@coreboot.org [101207 23:06]:
* Patrick Georgi patr...@georgi-clan.de [101207 16:35]:
Am 06.12.2010 23:45, schrieb Uwe Hermann:
See patch.
src/cpu/Kconfig defines CACHE_AS_RAM to !ROMCC, so I think these can
be dropped completely. Right?
We basically assume
On 12/7/10 10:00 PM, Peter Stuge wrote:
repository service wrote:
first round name simplification. drop the component_ prefix.
Beautiful.
+++ trunk/src/mainboard/advantech/pcm-5820/romstage.cWed Dec 8
06:42:47 2010(r6149)
@@ -27,7 +27,7 @@
#include
ready for an Ack?
Marc
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There is/used to be some code that sets the baud rate to coreboots default on
every SMM entry if SMM debug is enabled. Might mess up whatever the OS is doing
though, it's not recovering the OS specified values.
On 30.11.2010, at 09:35, Scott Duplichan sc...@notabs.org wrote:
From:
* Tobias Diedrich ranma+coreb...@tdiedrich.de [101128 11:43]:
Stefan Reinauer wrote:
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010
(r6127)
@@ -0,0 +1,101 @@
...
+DefinitionBlock (DSDT.aml, DSDT, 2, CORE
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010
(r6127)
@@ -0,0 +1,101 @@
...
+DefinitionBlock (DSDT.aml, DSDT, 2, CORE , COREBOOT, 1)
+{
+ /* Define the main processor.*/
+ Scope (\_PR)
+ {
+
On 11/26/10 2:28 PM, Uwe Hermann wrote:
See patch.
Uwe.
Since it's amd specific (in a sense that it's not much benefit and only
used on amd based boards), we should move it to cpu/amd/acpi or
cpu/amd/amdk8/acpi?
Stefan
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On 11/26/10 2:31 PM, Fontaine, Eric R wrote:
Dear Coreboot Developers,
I am very impressed with coreboot and agree with the importance of open
source firmware. I am looking at your list of supported server motherboards,
and see support for SuperMicro X6D series, but do not see any support
(thanks for the comments).
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de
Acked-by: Stefan Reinauer ste...@coreboot.org
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Acked-by: Stefan Reinauer ste...@coreboot.org
On 24.11.2010, at 14:05, Uwe Hermann u...@hermann-uwe.de wrote:
See patch.
Uwe.
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v4_mcp55_tinybootblock.patch
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coreboot
fine.
The Rachmann did suspend/resume support for Asus M2V he will post the
patch soon.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Awesome! Thanks a lot for cleaning up behind me ;)
Acked-by: Stefan Reinauer ste...@coreboot.org
Stefan
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On 11/21/10 3:37 PM, Uwe Hermann wrote:
i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc
chipsets. We did the same conversion on i440BX, i830, and others.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Stefan
On 11/21/10 11:55 PM, Qing Pei Wang wrote:
agree, actually the vga will show nothing about the booting message,
it's too fast.
Acked-by: QingPei Wangwangqing...@gmail.com
mailto:wangqing...@gmail.com
Thanks, Qing Pei, committed as r6111!
Stefan
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* repository service s...@coreboot.org [101122 14:07]:
Author: oxygene
Date: Mon Nov 22 14:07:10 2010
New Revision: 6113
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6113
Log:
Workaround to get die.c to work with romcc.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
* Bao, Zheng zheng@amd.com [101122 09:02]:
But there would be nothing on the screen if no payload is attached. That would
be confusing when the board is still in debug stage.
We might want to add an exception for this.
However, if the board is still in debug stage, a debug console (serial
On 11/21/10 4:34 PM, Tobias Diedrich wrote:
S3 support for ASUS M2V
This adds the board-specific parts for S3 support on the M2V board.
Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de
Nice! I'm surprised how small the patch is.
Acked-by: Stefan Reinauer ste...@coreboot.org
* Marc Jones marcj...@gmail.com [101119 00:55]:
Update coreboot crossgcc toolchain, GDB 4.5.1, MPFR 3.0.0, GDB 7.2.
Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
Add GDB patch to handle #pragma pack in the i386-elf gcc target.
Signed-off-by: Marc Jones marcj...@gmail.com
* Fengwei Zhang namedy...@gmail.com [101117 22:41]:
Hi all,
I am not sure if this is true. I just tried current coreboot source
tree (revision 6084) for ASUS M2V-MX SE, it cannot boot.
It could compile successfully, and it will be dead at the beginning
when booting.
Below are the info from
,
Fengwei
On 11/17/2010 06:08 PM, Stefan Reinauer wrote:
* Fengwei Zhangnamedy...@gmail.com [101117 22:41]:
Hi all,
I am not sure if this is true. I just tried current coreboot source
tree (revision 6084) for ASUS M2V-MX SE, it cannot boot.
It could compile successfully, and it will be dead
Should we rename the part to w83627 then?
Stefan
Sent from my mobile phone
On 16.11.2010, at 11:47, Uwe Hermann u...@hermann-uwe.de wrote:
See patch.
Uwe.
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