On 8/17/10 12:05 PM, Jens Rottmann wrote:
filo: 'make distclean' forgot to rm .xcompile
Added to Makefile.
Signed-off-by: Jens Rottmann jrottm...@lippertembedded.de
Thanks. r136
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On 8/16/10 9:18 AM, Qing Pei Wang wrote:
hi all,
tilapila support both dual slot and single slot. The difference
should be detected by the existence of dev3. Some other RS780
mainboard has
the same function. The patch added the function to make these boards
work smoothly.
Signed-off-by:
fine too. However it seems SATA has some
issues.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Stefan Reinauer ste...@coresystems.de
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Thanks for fixing coreboot. mainboard specific setup code is critical
for many boards.
Stefan
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On 8/16/10 6:11 PM, Stefan Reinauer wrote:
On 8/16/10 5:11 PM, Myles Watson wrote:
Index: src/devices/device.c
===
--- src/devices/device.c (revision 5692)
+++ src/devices/device.c (working copy)
@@ -1104,6 +1104,9
On 8/16/10 6:45 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
Thanks for fixing coreboot.
This was also why I acked. I think even if it's not what I would
like, it's how things work now, so better fix it. :)
mainboard specific setup code is critical for many boards.
What does it do
See patch
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sconfig
On 8/13/10 9:50 AM, Qing Pei Wang wrote:
hi,
the attach file added the support of Gigabyte MA785GMT mainboard.
the details of the hardware configuration can be found at
http://www.gigabyte.com/products/product-page.aspx?pid=3478
a breif configuration is:
1. CPU:Support for AM3 processors:
On 8/14/10 11:50 AM, Carl-Daniel Hailfinger wrote:
On 14.08.2010 11:40, Stefan Reinauer wrote:
On 8/12/10 9:27 PM, Patrick Georgi wrote:
1. [...]
This one looks for the size of .bss and .data (initialized and
uninitialized globals) and breaks the build if it finds any. It doesn't
tell
On 8/14/10 12:40 PM, Carl-Daniel Hailfinger wrote:
On 14.08.2010 12:24, Stefan Reinauer wrote:
On 8/14/10 11:50 AM, Carl-Daniel Hailfinger wrote:
On 14.08.2010 11:40, Stefan Reinauer wrote:
On 8/12/10 9:27 PM, Patrick Georgi wrote:
1. [...]
This one looks
On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote:
The attached patch adds a register table for the IT8500 embedded
controller. Here is a sample of the output:
superiotool r5679
[..]
Signed-off by: Donald Huang (donald.hu...@ite.com.tw
mailto:donald.hu...@ite.com.tw)
Signed-off by:
set of those calls to make
the functions quit after a chip is found.
Great catch.
Signed-off by: David Hendricks (dhend...@google.com
mailto:dhend...@google.com)
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 8/10/10 3:24 PM, ali hagigat wrote:
ljmp $ROM_CODE_SEG, $protected_stage0
Where is the definition of the symbol, protected_stage0?
Thank you to read my message.
The file you are looking at, src/arch/i386/init/entry.S is unused. The
file was supposed to replace
On 8/10/10 5:06 PM, ali hagigat wrote:
update:
dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
What was dongle.py in top makefile?
It's the program controlling this: http://www.coreboot.org/FlexyICE
Unless you have one of those you don't need to worry.
Stefan
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On 8/9/10 2:16 PM, Peter Stuge wrote:
repository service wrote:
non-root devices are not supposed to be accessed outside of
static.c except by walking the tree.
Hmm, how does this fit with the gx2/lx code that looks for 5536, or
if it was the other way around?
All device operations within
On 8/4/10 2:58 AM, Peter Stuge wrote:
Hi,
silversurfer.2...@gmx.de wrote:
I bought the PLX NET20DC USB Debug Device.
Now I want to use this device for debug purpose. But I get with
different mainboards the same build error messages.
Can anybody help?
This code hasn't been exercised in
On 8/4/10 8:00 PM, Myles Watson wrote:
And the patch.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 8/2/10 5:14 PM, repository service wrote:
Author: myles
Date: Mon Aug 2 17:14:13 2010
New Revision: 5680
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5680
Log:
Build VGA code conditionally to avoid errors when using SeaBIOS.
Signed-off-by: Myles Watson myle...@gmail.com
On 8/2/10 2:59 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any
user /
board porter: printk should always be available in CAR mode.
Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board but
it's
See patch
- Drop lots of dead code from the various cache_as_ram.inc files.
- Use some descriptive macros instead of magic numbers for MTRR MSRs
- slightly reformatting code and comments
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===
--- src/cpu/intel/model_6ex/cache_as_ram.inc(revision 5682)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc(working copy
On 02.08.2010, at 12:43, xdrudis xdru...@tinet.cat wrote:
On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote:
When I boot with the propietary BIOS I can get GRUB2 and linux console
on the serial port, but only at 38400 bps. 118000 does not work. So
I've put 38400 in kconfig too.
On 8/1/10 7:13 AM, austi...@msu.edu wrote:
Hi.
The wiki page for seabios recommends configuring coreboot with
CONFIG_VGA_BRIDGE_SETUP enabled and CONFIG_VGA_ROM_RUN disabled.
When building for the jetway j7f24 target, setting those two options
in menuconfig results in the following error
Original Message
Subject:Re: [coreboot] coreboot halts at doing early_mtrr
Date: Sun, 01 Aug 2010 17:28:41 +0200
From: Stefan Reinauer stefan.reina...@coresystems.de
Organization: coresystems GmbH
To: Corey Osgood corey.osg...@gmail.com
On 8/1/10 5:10 AM
This patch resulted from a security review of coreboot's SMM handler.
Feedback appreciated.
Regards,
Stefan
- fix SMM code relocation race
- make SMM relocation debugging Kconfig accessible
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/intel/i82801dx
no
comparison though.
Stefan
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On 7/26/10 9:28 PM, Myles Watson wrote:
I was thinking of some of the ACPI code, that is not
mainboard-dependent but chipset-dependent. That's been slowly moving
to the chipset directories.
If we can get rid of exceptions by cleaning more code up in this way we
should certainly do it.
On 7/20/10 8:17 AM, Vitaly Chertovskih wrote:
Hi!
I'm experiencing some troubles in installing coreboot on Roda RK886EX.
Please, help me.
Is there some manual about installation coreboot on Roda?
I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS
image (I download it
On 7/12/10 10:47 AM, Takuo Fukunaga wrote:
Hi, my apologies in advance for the newbie question.
I would just like to know what information is necessary to
support recent Intel chipsets such as Nehalem chipsets.
Datasheets for these chipsets are available on Intel's
web site and I think
On 7/8/10 8:09 PM, Myles Watson wrote:
On Thu, Jul 8, 2010 at 11:56 AM, Patrick Georgi patr...@georgi-clan.de
wrote:
Am 08.07.2010 19:50, schrieb Myles Watson:
BOOTBLOCK_NORMAL allows the user to use CMOS values to select which
image to boot. This patch:
- makes BOOTBLOCK_NORMAL depend
On 7/9/10 6:01 PM, Myles Watson wrote:
On Fri, Jul 9, 2010 at 9:55 AM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 7/9/10 3:36 PM, Myles Watson wrote:
On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge pe...@stuge.se wrote:
Stefan Reinauer wrote:
Even though the normal/fallback
See patch
become more standard with libpayload headers. PATH_MAX belongs in limits.h,
tiny curses can use standard includes now.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: include/limits.h
===
--- include/limits.h
On 7/9/10 8:35 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
1. Should Fallback always ignore CMOS? I think it would make more sense
if Normal and Fallback were the same and both would write a decent set
of CMOS defaults in the case of a bad checksum.
NAK if this means that testing coreboot
On 7/7/10 6:42 AM, ali hagigat wrote:
My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
First question:
I wonder how PCI memory read cycles can read an instruction from
F000:FFF0 right after reset which is the first instruction of BIOS.
x86 CPUs are designed like that. Go read the
On 7/7/10 12:44 PM, ali hagigat wrote:
Stefan,
BIOS chip is not connected to CPU directly after reset!!
It's never connected directly, anyways, but through some kind of bridge.
Usually the southbridge.
I mean the hardware immediately accesses BIOS chip after reset
but at
On 7/6/10 11:05 PM, Myles Watson wrote:
On Wed, Jun 30, 2010 at 11:52 AM, Edwin Beasant
edwin_beas...@virtensys.com wrote:
Seems best of all worlds to me :-)
Can we get an ack and a commit?
Rev 5653.
Thanks,
Myles
Not sure why there were no errors, but:
9
On 7/7/10 1:04 PM, ali hagigat wrote:
Is Coreboot source code is a position independent code? I mean, will
it be executed from any arbitrary location of the main memory?
Most of it, no.
Can it be revoked and correctly executed by a bootloader like Grub if
I make a binary image of it and
/
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On 7/7/10 4:56 PM, Myles Watson wrote:
Kill a few more warnings.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Acked-by: Stefan Reinauer ste...@coresystems.de
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Hi,
I suggest applying the following patch to encourage folks to get their
warnings fixed and cleaned up.
Stefan
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/Kconfig
===
--- src/Kconfig (revision 5655)
+++ src
On 7/7/10 8:28 PM, Myles Watson wrote:
On Wed, Jul 7, 2010 at 8:24 AM, Myles Watson myle...@gmail.com wrote:
Rev 5653.
Thanks,
Myles
Not sure why there were no errors, but:
9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No
such file or directory
That's odd. I
://www.coresystems.de/
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On 6/30/10 4:16 PM, Carl-Daniel Hailfinger wrote:
15kb lzma compressed is nothing.
8 kB more or less in a recovery payload of a coreboot image are not
negligible IMHO.
In normal OS environments people don't use compressed binaries, and
there a 2 MB size increase for flashrom (98%
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already set by the compiler?
Anyways,
Acked-by: Stefan Reinauer ste...@coresystems.de
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With the issue fixed,
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On 6/21/10 12:15 PM, Joseph Smith wrote:
On Mon, 21 Jun 2010 11:48:33 +0200, Peter Stuge pe...@stuge.se wrote:
Joseph Smith wrote:
Before I did not get the Using generic cpu ops (good) is that ok?
The message seems to suggest so..
Hmm, to me it suggests it is
On 6/21/10 7:24 PM, Joseph Smith wrote:
Why print out a generic message?
I think it just means not-stepping-specific
I like your verbage alot better than generic.
Or even default would be better than generic.
So, any native speakers with a good suggestion how the text
, %dMB IGD UMA\n, igd_memory 10);
+ }
You might want to read the SMRAM register intead of relying on the
setting of the config variable in case an invalid value sneaked in.
Other than that:
Acked-by: Stefan Reinauer ste...@coresystems.de
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caveats:
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/Kconfig
===
--- src/cpu/intel/Kconfig (revision 5634)
+++ src/cpu/intel/Kconfig (working copy)
@@ -17,6 +18,7 @@
source src/cpu/intel
...@settoplinux.org
Acked-by: Stefan Reinauer ste...@coresystems.de
with some caveats:
Index: src/mainboard/intel/d810e2cb/gpio.c
===
--- src/mainboard/intel/d810e2cb/gpio.c (revision 0)
+++ src/mainboard/intel/d810e2cb
On 20.06.2010, at 14:44, Joseph Smith j...@settoplinux.org wrote:
On 06/20/2010 07:46 AM, Stefan Reinauer wrote:
On 6/20/10 10:04 AM, Joseph Smith wrote:
Hello,
This patch adds a new socket for FCPGA370 and PGA370 CPU's. This new
socket (called socket_FC_PGA370) will make the CAR transition
On 6/19/10 6:47 PM, Christian Ruppert wrote:
On 06/19/2010 04:05 PM, bari wrote:
Wang,
If you need any AMD 7xx boards donated to your GSOC project that are
only available in Europe or USA, please let us know.
-Bari
That sounds great!
Please take a look at the Asus M4A79XTD EVO
On 6/19/10 11:48 PM, Cristi Magherusan wrote:
See attached patch.
I had to add that ifdef because config.h didn't have defined the
CONFIG_USBDEBUG_DIRECT option and compilation failed.
If anyone has an idea how I can get it defined there, I'm all ears.
Why not just leave it as it is?
On 6/17/10 3:15 AM, GS Hunt wrote:
I noticed that there is still a request for AMD740G chipset info almost
a year later after I first posted some info regarding it. Is it in limbo
now?
I doubt anybody was ever working on this. There is, however, support for
AMD's RS780 chipset which might
On 6/17/10 5:12 PM, Myles Watson wrote:
It looks like Patrick found this before:
http://www.coreboot.org/pipermail/coreboot/2009-November/054387.html
If I take out the free it works fine. It seems like there must be a better
fix.
Agreed.
I took a look at this a little bit with
Great, thank you.
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello,
I have a strange thing happening on the i810 port I am working on. When I
power the board on i do not get any serial console from coreboot. VGA turns
on and works fine, but no serial output. The strange part is if I push the
reset button, serial
On 6/15/10 2:25 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 14:13:24 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello,
I have a strange thing happening on the i810 port I am working on. When
I
power the board
On 6/15/10 2:41 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 05:30:07 -0700, ron minnich rminn...@gmail.com wrote:
It would seem that the RAM code is right but the early setup code is
wrong. It's working because the early setup is probably having no
effect whatsoever ...
Hmm,
On 6/15/10 4:07 PM, Joseph Smith wrote:
When
I cold boot it, if I hit the reset button before Linux starts, it restarts
with coreboot serial console just fine.
Hm...
Maybe 0x2e/0x4e are mapped to LPC after the SuperIO is configured (and
that mapping survives a reset)... that would be a
On 6/15/10 4:28 PM, Joseph Smith wrote:
Hmm, This is interesting. The first time I booted it, I had copied romstage
from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it came
to detecting and
On 6/16/10 12:37 AM, Joseph Smith wrote:
But there is one other small issue. Looks like the resource allocater
is not allocating any space for device 43.a the Runtime Registers.
My devicetree.cb looks like:
device pnp 4e.a on# Runtime registers
io 0x60 =
On 6/12/10 4:05 PM, Joseph Smith wrote:
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base:0MB, range: 128MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable
See Patch.
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- Use
: Stefan Reinauer • Ust-IdNr.: DE245674866
Add VGA hooks to operate the following mainboards with coreboot + SeaBIOS:
- Kontron 986LCD-M
- Getac P470 (Laptop)
- Roda RK886EX (Laptop)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
--- src/vgahooks.c
+++ src/vgahooks.c
@@ -17,6 +17,23
See patch
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On 6/9/10 1:57 AM, Anders Jenbo wrote:
This patch adds the ECS P6IWP-Fe board to coreboot.
Signed-off-by: Anders Jenbo and...@jenbo.dk
Thanks a lot!
Acked-by: Stefan Reinauer ste...@coresystems.de
and checked in as r5623
But please add a license header to the device tree as well in an extra
(0xcf8-0xcff) and some other fixed
resources that might live down there (smbus base, acpi base,...)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/via/vt8231/vt8231_lpc.c
===
--- src/southbridge/via/vt8231
On 09.06.2010, at 12:47, Joseph Smith j...@settoplinux.org wrote:
On Wed, 09 Jun 2010 10:09:21 +0200, Stefan Reinauer ste...@coresystems.de
wrote:
On 6/9/10 1:57 AM, Anders Jenbo wrote:
This patch adds the ECS P6IWP-Fe board to coreboot.
Signed-off-by: Anders Jenbo and...@jenbo.dk
On 6/9/10 7:54 PM, Joseph Smith wrote:
On Wed, 09 Jun 2010 09:45:28 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
SeaBIOS VGA hooks for Getac P470 and Roda RK886EX notebooks
This is awsome!
Acked-by: Joseph Smith j...@settoplinux.org
Any chance for a SMI Handler
On 6/9/10 8:00 PM, Myles Watson wrote:
On Wed, Jun 9, 2010 at 1:45 AM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
SeaBIOS VGA hooks for Getac P470 and Roda RK886EX notebooks
It seems surprising to want to make SeaBIOS have this much stuff
that's board-specific.
int15
On 6/9/10 8:11 PM, Joseph Smith wrote:
On Wed, 09 Jun 2010 19:55:36 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 6/9/10 7:54 PM, Joseph Smith wrote:
On Wed, 09 Jun 2010 09:45:28 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
SeaBIOS VGA
the same description text for CD and DVD drives all over the tree.
- Mention DVD first as it's more likely these days
- capitalize Rom since it's an abbreviation
Signed-off-by: Stefan Reinauer ste...@coresystems.de
--- src/ata.c
+++ src/ata.c
@@ -774,7 +774,7 @@
snprintf(adrive_g-drive.desc
On 6/9/10 8:48 PM, Myles Watson wrote:
It would need to be 0xe - 0xf unless we want to start cutting
out more memory.
I meant where as in what interrupt to patch, not what address to run
at. SeaBIOS should be able to use whatever address it wants to.
If it contains a
On 6/9/10 10:15 PM, Joseph Smith wrote:
The coreboot SMI handler already implements that. Remember SMI handlers
stay active even when the OS is loaded.
For security reasons coreboot even locks SMM so that SeaBIOS (or a Linux
kernel module or root process) couldn't just install a new handler.
On 6/9/10 11:03 PM, Joseph Smith wrote:
Ok cool. Then I guess SeaBIOS just needs to be able to load vga bios
and mbi rom. Correct?
Not even that complicated. mbi is loaded by coreboot, so SeaBIOS has
everything it needs. It might at some point need a mainboard specific
int15 handler, if that
On 6/9/10 11:49 PM, Myles Watson wrote:
Signed-off-by: Myles Watson myle...@gmail.com
Removed some warnings and fixed static.c generation when the
southbridge link is not 0.
I didn't test this, but assuming we're not planning on getting rid of
malloc anymore, this is
Acked-by: Stefan
On 6/10/10 12:27 AM, Myles Watson wrote:
On Wed, Jun 9, 2010 at 4:14 PM, Stefan Reinauer ste...@coresystems.de wrote:
On 6/9/10 11:49 PM, Myles Watson wrote:
Signed-off-by: Myles Watson myle...@gmail.com
Removed some warnings and fixed static.c generation when the
southbridge link
On 6/8/10 10:55 AM, Антон Кочков wrote:
+static void enter_conf_mode_ite_it8502e(uint16_t port)
+{
+ OUTB(0x85, port);
+ OUTB(0x02, port);
+ OUTB(0x55, port);
+ OUTB((port == 0x2e) ? 0x55 : 0xaa, port);
+}
+
This one looks kind of weird... Do you have a datasheet
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On 6/8/10 12:55 AM, Nils wrote:
+ __builtin_wrmsr(MSR_GLIU1_SYSMEM, 0x6bf00100, 0x201f); /*
0x10-0x1F6BF000 */
Why 1F6BF000 ?
Stefan
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On 6/8/10 12:47 PM, Joseph Smith wrote:
That error message is in the linux decompression code and appears when
it can't malloc the necessary memory (32kb), or if it's asked to
decompress to address 0.
I guess that this either means that linux doesn't find usable memory
tables, or that some
-
From: coreboot-bounces+edwin_beasant=virtensys@coreboot.org
[mailto:coreboot-bounces+edwin_beasant=virtensys@coreboot.org] On Behalf
Of ron minnich
Sent: 06 June 2010 05:50
To: Myles Watson
Cc: Stefan Reinauer; coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix geode lx
on UHCI. It's
of not much use on the other controllers.
It requires a copy of uhci.h to uhci_private.h
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 6/6/10 5:01 PM, Rudolf Marek wrote:
Hello,
It makes me wonder why CAR on APs use same stack?
Maybe it is not coherent?
Or maybe it doesn't really work?
I see that Fam10h CAR
code allocates 1KB for each AP. But not pre Fam10h.
How this can work?
Rationale for question is to have some
On 6/6/10 5:42 PM, Rudolf Marek wrote:
I think it is mostly because there is memory init done by APs. Is this
true for
some board?
Afaik it's ECC clearing which is implemented several times in the
tree, including stage2.
It needs no PCI access nor console output, though... and parallelizing
the
On 6/6/10 6:29 PM, Rudolf Marek wrote:
Afaik it's ECC clearing which is implemented several times in the
tree, including stage2.
Nope, the APs can init the memory controller too. Check
CONFIG_MEM_TRAIN_SEQ 0 for BSP only
1 = train_ram_on_node is called from init_cpus
2 = dunno - looks
On 6/5/10 5:15 AM, Tiago Marques wrote:
See the attachment, doesn't look like something from a company that's
alive and kicking. I know them since the SiS 730.
Last time I heard they had some design win for a Core 2 chipset that I
haven't seen in any product and started selling SiS branded
. Brahmsstr. 16 . D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 . Fax: +49 761 7664613
Email: i...@coresystems.de . http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg . HRB 7656
Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866
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See patch
Warn if resources could not be assigned.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/devices/device.c
===
--- src/devices/device.c(revision 5568)
+++ src/devices/device.c(working copy
of the patch with those issues fixed (and pushing
one register instead of all), see attachment
Signed-off-by: Edwin Beasant edwin_beas...@virtensys.com
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/devices/oprom/x86_asm.S
On 6/4/10 6:36 PM, Myles Watson wrote:
if (!(res-flags IORESOURCE_FIXED))
continue;
...
/* Is it already outside the limits? */
- if (((res-base + res-size -1) lim-base) || (res-base
lim-limit))
+ if (((res-base
On 6/4/10 6:40 PM, Stefan Reinauer wrote:
On 6/4/10 6:37 PM, Patrick Georgi wrote:
Am Freitag, den 04.06.2010, 16:25 +0100 schrieb Edwin Beasant:
This patch fixes the option rom code that was buggy when it switched
segment registers before restoring register values
See patch
mostly cosmetical. don't use movw because we use mov in most places.
Also, drop some dead code at the very end where some segment registers
get set up and are immediately overwritten by pops.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/devices/oprom/x86_asm.S
On 6/3/10 8:24 AM, Bao, Zheng wrote:
The code was ported. Now it is what it should be.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/amd/rs780/rs780_gfx.c
On 6/3/10 7:28 PM, mbertens wrote:
On Wed, 2010-06-02 at 16:49 -0400, Joseph Smith wrote:
On 06/02/2010 03:08 PM, Marc Jones wrote:
On Wed, Jun 2, 2010 at 10:54 AM, mbertensmbert...@xs4all.nl wrote:
Hi all,
i wrote a document how to flash an Nokia IP530, it can be found at
See patch.
libpayload: Add function to fix CMOS checksum.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: include/libpayload.h
===
--- include/libpayload.h(revision 5606)
+++ include/libpayload.h(working
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