Re: [coreboot] [PATCH EHCI Debug Port setup for all AMD SB600/SB700 boards

On 9/24/10 7:16 PM, ron minnich wrote: > On Fri, Sep 24, 2010 at 8:43 AM, Stefan Reinauer > wrote: > >> We could do a lot of such or similar improvements if we started not >> including code but adding it to an object list. >> >> Who's gonna do it? > Firs

Re: [coreboot] [PATCH EHCI Debug Port setup for all AMD SB600/SB700 boards

infrastructure. > > Without a (currently) dummy set_debug_port() function the build fails, > this may or may not be fixed differently in the future. > > Manually build-tested on all SB600/SB700 boards, and tested on hardware on > one SB600 board I own, works fine. > > Signed-

Re: [coreboot] [PATCH EHCI Debug Port setup for all AMD SB600/SB700 boards

On 9/23/10 11:39 PM, Peter Stuge wrote: >> +#if CONFIG_USBDEBUG >> +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" >> +#include "pc80/usbdebug_serial.c" >> +#endif > Can this go somewhere outside the mainboard directory? > > If anything does need to go in the mainboard dir now, then woul

[coreboot] [PATCH] fix option table race (this time for real)

e.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer Index: src/include/pc80/mc146818rtc.h === --- src/include/pc80/mc146818

Re: [coreboot] [commit] r5823 - in trunk: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/main

On 9/21/10 11:37 PM, ron minnich wrote: > On Tue, Sep 21, 2010 at 2:16 PM, repository service wrote: >> Author: uwe >> Date: Tue Sep 21 23:16:27 2010 >> New Revision: 5823 >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5823 >> >> Log: >> Cut the crap. > > Just FYI the history of thi

Re: [coreboot] [PATCH] [RFC] sata PHY settings callback on SB700

orted.\n"); } Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE2

Re: [coreboot] ohava laptop coreboot

On 9/20/10 5:26 AM, Sahil Sinha wrote: I spoke with someone in the IRC to send this here, I offered free hardware for a port of coreboot to this machine. Can you also provide the necessary RS-NDAed Intel data sheets for the chipset? (I.e. not the stuff on the public web page) Stefan -- coreb

Re: [coreboot] [PATCH] cbfstool "add-lzma" method

On 9/6/10 5:27 PM, Kevin O'Connor wrote: > I've also been thinking of adding another helper - "add-string". So a > user could do something like: "cbfstool ROM add-string '5500' > cfg/boot-menu-delay". As I think this may be a straight forward way > to pass simple config items into SeaBIOS. What'

Re: [coreboot] AMD cache setup is broken (was: SuperMicro h8dmr-i2 slowness in v4)

On 9/6/10 10:12 AM, Arne Georg Gleditsch wrote: > "Nick Lemberger" writes: >> Hello, >> >> I'm having some trouble with current releases of coreboot on a >> Supermicro H8DMR-i2. >> >> The initial problem, it takes about 2 minutes to show the: >> "coreboot-4.0-r5775 Fri Sep 3 14:55:01 CDT 2010 st

Re: [coreboot] [PATCH] fix 'AMD Fam10 code breaks with gcc 4.5.0'

t; Signed-off-by: Scott Duplichan With the explanation above added to each of the two files, this is Acked-by: Stefan Reinauer However, I think we should additionally look at "fixing" AMD's CAR code to not call C functions with neither CAR or RAM backing them. I reworked all

Re: [coreboot] Question about did my MB is supported

On 9/6/10 9:33 AM, Condor wrote: > Hello all, > i read information on the coreboot site but i still doubt did my MB is > supported. I expect to run Linux with lilo and Windows 7 32 bit. > > Here is information for my MB answering questions from FAQ: Will coreboot > work on my machine? > > # lspci

Re: [coreboot] filo prompt, how to access usb disk?

On 9/5/10 6:23 PM, BeBa wrote: > Hi, > I just flashed a ga-6bxc and find no way to access its usb sticks. > Filo has been compiled with IDE_NEW_DISK and USB_STACK. > filo> kernel uda1:/vmlinuz > spits out: File not found. This means that there is no file with that name on the first USB device.

Re: [coreboot] [commit] r5775 - in trunk/src/mainboard/lippert: roadrunner-lx spacerunner-lx

On 9/3/10 5:16 PM, repository service wrote: >device pnp 2e.7 on # GPIO > -io 0x62 = 0x1220 > -io 0x64 = 0x1200 > +io 0x62 = 0x1220 # Simple I/O > +io 0x64 = 0x1228 # SPI >end Are these IO ports? If so, you might be se

Re: [coreboot] [PATCH] option_table.h race

On 9/1/10 5:26 PM, Myles Watson wrote: > The only thing that worries me is this include. > > from src/include/pc80/mc146818rtc.h: > #include > > It seems like usually when we make initobj, we stop including the c file. Yes... Another problem though. It's guarded by #ifdef __ROMCC__ so it only ge

[coreboot] device tree rework (was: Re: [PATCH] use Kconfig for both options on Lippert boards)

Peter Stuge wrote: > Jens Rottmann wrote: >>> Maybe make that one option per port instead, >> I had considered this but decided against it. > Oh well. > > >> It is simply not feasible to make _everything_ configurable, > I'm not sure I agree about feasible. I agree it's not worthwhile > though. Yo

Re: [coreboot] [PATCH] use Kconfig for both options on Lippert boards

eiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] option_table.h race

p the AMD DBM690T work around for the issue. Signed-off-by: Stefan Reinauer Index: src/include/pc80/mc146818rtc.h === --- src/include/pc80/mc146818rtc.h (revision 5761) +++ src/include/pc80/mc146818rtc.h (working copy) @@ -

Re: [coreboot] (no subject)

On 8/31/10 7:29 AM, Bao, Zheng wrote: > Get Byte65/66 for register manufacture ID code. RegMan1Present will > be used in write levelization training. > > Signed-off-by: Zheng Bao Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. T

[coreboot] [PATCH] CACHE_AS_RAM

See patch We call this cache as ram everywhere, so let's call it the same in Kconfig Signed-off-by: Stefan Reinauer Index: include/assert.h === --- include/assert.h(revision 5749) +++ include/assert.h(working

Re: [coreboot] [PATCH] restructure mainboard Kconfigs

On 8/30/10 5:47 PM, Jens Rottmann wrote: > Hi, > >> In my last mail I described some restructuring to make (user visible) options >> in the board specific Kconfig files possible (i.e. don't source from within >> choice/endchoice). Another change I'd like to add is to move MAINBOARD_VENDOR >> and M

Re: [coreboot] [PATCH 3/3] support for Lanner EM-8510 Board

On 8/30/10 12:10 PM, Andreas Schultz wrote: > Signed-off-by: Andreas Schultz Dear Andreas, glad to see you had some success with coreboot! thank you very much for your contributions! I checked in your patches in r5750-r5753 Best regards, Stefan -- coreboot mailing list: coreboot@coreboot.o

Re: [coreboot] util directory

> Inside util/abuild we have two files: abuild and abuild.1 > > What language do they have written with? abuild is a shell script. abuild.1 is a man page > What is their functions in short? Find out yourself by typing man ./abuild.1 in the abuild directory. > Are they necessary for building a cor

Re: [coreboot] AMD ddr MCT channelB patch

> > Hi, > > > > Multi-DIMMS on AMD ddr MCT channel B fixed. > > > > Signed-off-by: Kerry She mailto:kerry....@amd.com>> > > > Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] amd-mct_ddr3-ChannelB Patch

On 8/30/10 8:50 AM, She, Kerry wrote: > > Hi, > > > > Multi-DIMMS on AMD ddr3 MCT channel B works. > > > > Signed-off-by: Kerry She > > > Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] mainboard.c: init() still being called?

burg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Kconfig: convert dependency lists into HAVE_x properties

13 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [inteltool] added initial support of CPU extended information and non-Intel CPU's

On 8/25/10 7:34 PM, Антон Кочков wrote: > inteltool: added initial support of cpu_info extended information > inteltool: added initial support for other cpu's > inteltool: dumping MSR registers for Intel Celeron M 743 > Signed-off-by: Anton Kochkov Hi Anton, just some thoughts... I don't think

[coreboot] [PATCH] Fix i945 port

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Fix

Re: [coreboot] Trouble linking coreinfo payload

On 8/23/10 6:19 AM, Andrew Guertin wrote: > I'm having trouble building the coreinfo payload, at the linking stage. > > I've checked out a fresh copy of the coreboot repository from svn. > I've then run the following commands: > > cd payloads/libpayload/ > make menuconfig (accepted defaults) > mak

Re: [coreboot] [PATCH] move PHY fine tune to devicetree.cb

On 8/23/10 12:24 AM, Carl-Daniel Hailfinger wrote: > On 22.08.2010 23:41, Patrick Georgi wrote: >> Am 22.08.2010 23:38, schrieb Stefan Reinauer: >> >>> Shouldn't such values rather go into the mainboard specific code (ie an >>> array in m

Re: [coreboot] [PATCH] move PHY fine tune to devicetree.cb

On 8/22/10 10:37 PM, Rudolf Marek wrote: > Index: src/mainboard/amd/mahogany/devicetree.cb > === > --- src/mainboard/amd/mahogany/devicetree.cb.orig 2010-08-22 > 11:54:20.0 +0200 > +++ src/mainboard/amd/mahogany/devicetre

Re: [coreboot] [PATCH] remove unused devicetree.cb entries

On 8/22/10 10:39 PM, Rudolf Marek wrote: > Hello > > Following patch removes unused ide0_enable and sata0_enable entries > from SB7xx and SB600. > > Untested. > > Signed-off-by: Rudolf Marek Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] [commit] r5717 - in trunk/src/superio/fintek: . f71863fg

On 8/19/10 2:55 AM, Qing Pei Wang wrote: > Signed-off-by: Wang Qing Pei > Thanks. r5737 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] ht init and some errata for AMD fam 10 RB_C3

On 8/22/10 9:46 PM, Stefan Reinauer wrote: > On 8/19/10 11:52 PM, xdrudis wrote: >> My smallest patch ever > will be applied after sign-off :-) > Ah, missed the sign-off in the extra mail. It's in. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.

Re: [coreboot] [PATCH] ht init and some errata for AMD fam 10 RB_C3

On 8/19/10 11:52 PM, xdrudis wrote: > My smallest patch ever will be applied after sign-off :-) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] superiotool: Add suport for normal register dumping on ite8510E/TE/G

On 8/22/10 4:45 AM, Anders Juel Jensen wrote: > Add suport for normal register dumping on ite8510E/TE/G > > Signed-off-by: Anders Juel Jensen > > I am going to add support for --extra-dump when i grok the data sheet a > little > better Unless someone beats me to it ;-) Thanks a lot! I comm

Re: [coreboot] Abit AX8 - Support

On 8/22/10 2:44 AM, mama fua wrote: > Hello, it's my first e-mail here on coreboot mailing list. I would > like to ask if there is someone already working or interested on > supporting the mainboard Abit AX8. It has these components: > > -Socket 939 > -Northbridge K8T890 > -Southbridge VT8237 > -S

Re: [coreboot] Coreboot and stand alone filo

is what i don't want > to use Why? > , is there any other version which doesn't requir coreboot/payload/payloadlib? > Yes but you will have to fix it yourself, as I wrote in the other mail.. > mv.h > > /Masoud > -Original Message- > From: Stefa

Re: [coreboot] Coreboot and stand alone filo

On 8/17/10 10:05 PM, Masoud Fatollahy wrote: > Hi, > > I am trying to make coreboot v4 works with a old version of filo(stand > alone). > > I build the coreboot and definde a paload which has been build with an > old filo which is not using payloadlib of the coreboot. > when filo try to read

Re: [coreboot] [PATCH] tidy up Asrock 939A785GMH

nd of better. > > The classic PCI slot works fine too. However it seems SATA has some > issues. > > Signed-off-by: Rudolf Marek Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] RS780 dev3 detection

On 8/16/10 9:18 AM, Qing Pei Wang wrote: > hi all, > tilapila support both dual slot and single slot. The difference > should be detected by the existence of dev3. Some other RS780 > mainboard has > the same function. The patch added the function to make these boards > work smoothly. > > Signed-

Re: [coreboot] [filo] [PATCH trivial] 'make distclean' forgot to rm .xcompile

On 8/17/10 12:05 PM, Jens Rottmann wrote: > filo: 'make distclean' forgot to rm .xcompile > > Added to Makefile. > > Signed-off-by: Jens Rottmann Thanks. r136 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] sconfig parser bug fixes

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 sconfig

Re: [coreboot] mainboard.c: init() still being called?

On 8/16/10 7:11 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >>>> mainboard specific setup code is critical for many boards. >>> What does it do? >> On some boards it sets up the fans. >> On others it makes sure the display brightness is initialized >>

Re: [coreboot] mainboard.c: init() still being called?

On 8/16/10 6:45 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >> Thanks for fixing coreboot. > This was also why I acked. I think even if it's not what I would > like, it's how things work now, so better fix it. :) > > >> mainboard specific setup code is cri

Re: [coreboot] mainboard.c: init() still being called?

On 8/16/10 6:11 PM, Stefan Reinauer wrote: > On 8/16/10 5:11 PM, Myles Watson wrote: >> Index: src/devices/device.c >> === >> --- src/devices/device.c (revision 5692) >> +++ src/devices/device.c (

Re: [coreboot] mainboard.c: init() still being called?

alize everything. */ > for (link = dev_root.link_list; link; link = link->next) > init_link(link); Acked-by: Stefan Reinauer Thanks for fixing coreboot. mainboard specific setup code is critical for many boards. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] mainboard.c: init() still being called?

end # Northbridge Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE2

Re: [coreboot] K8 SMP broken?

c creates a working image for you? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust

Re: [coreboot] [PATCH] Gigabyte MA785GMT support

On 8/13/10 9:50 AM, Qing Pei Wang wrote: > hi, > the attach file added the support of Gigabyte MA785GMT mainboard. > the details of the hardware configuration can be found at > http://www.gigabyte.com/products/product-page.aspx?pid=3478 > a breif configuration is: > 1. CPU:Support for AM3 proces

Re: [coreboot] global variables in romstage

On 8/14/10 12:40 PM, Carl-Daniel Hailfinger wrote: > On 14.08.2010 12:24, Stefan Reinauer wrote: >> On 8/14/10 11:50 AM, Carl-Daniel Hailfinger wrote: >> >>> On 14.08.2010 11:40, Stefan Reinauer wrote: >>> >>>> On 8/12/10 9:27 PM, Patr

Re: [coreboot] global variables in romstage

On 8/14/10 11:50 AM, Carl-Daniel Hailfinger wrote: > On 14.08.2010 11:40, Stefan Reinauer wrote: >> On 8/12/10 9:27 PM, Patrick Georgi wrote: >> >>> 1. [...] >>> This one looks for the size of .bss and .data (initialized and >>> uninitialized globals

Re: [coreboot] global variables in romstage

error message on what is wrong, inszead of the more cryptic one saying that a variable is defined in a discarded section. > There might also be a good opportunity for some naming cleanup: > Rename and move ldscript_fallback_cbfs.lb to > src/arch/i386/coreboot_rom.ld. Or better call it "rom

Re: [coreboot] dongle.py!!

On 8/10/10 5:43 PM, ali hagigat wrote: > My main questions are not answered! Maybe people think you should ask general GNU make questions to the GNU make developers or read the GNU make documentation. > Starting from top makefile, what is first rule that is executed? The first one in the top leve

Re: [coreboot] dongle.py!!

On 8/10/10 5:06 PM, ali hagigat wrote: > update: > dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF > > What was dongle.py in top makefile? It's the program controlling this: http://www.coreboot.org/FlexyICE Unless you have one of those you don't need to worry. Stefan -- coreboot mai

Re: [coreboot] Coreboot-v4 and protected_stage0?

On 8/10/10 3:24 PM, ali hagigat wrote: > ljmp $ROM_CODE_SEG, $protected_stage0 > > Where is the definition of the symbol, protected_stage0? > > Thank you to read my message. > > The file you are looking at, src/arch/i386/init/entry.S is unused. The file was supposed to replace src/cpu/x86/16bit/e

Re: [coreboot] [PATCH][superiotool] Quit probe_idregs_* early if chip_found is set

a simple check after each set of those calls to make > the functions quit after a chip is found. Great catch. > Signed-off by: David Hendricks (dhend...@google.com > <mailto:dhend...@google.com>) Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support

On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote: > > The attached patch adds a register table for the IT8500 embedded > controller. Here is a sample of the output: > > superiotool r5679 > [..] > > Signed-off by: Donald Huang (donald.hu...@ite.com.tw > ) > > Signed

Re: [coreboot] [commit] r5686 - trunk/util/sconfig

On 8/9/10 2:16 PM, Peter Stuge wrote: > repository service wrote: >> non-root devices are not supposed to be accessed outside of >> static.c except by walking the tree. > Hmm, how does this fit with the gx2/lx code that looks for 5536, or > if it was the other way around? All device operations wi

Re: [coreboot] Enable USB Debug Device!

On 8/4/10 8:00 PM, Myles Watson wrote: > And the patch. > > Signed-off-by: Myles Watson Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Enable USB Debug Device!

On 8/4/10 2:58 AM, Peter Stuge wrote: > Hi, > > silversurfer.2...@gmx.de wrote: >> I bought the "PLX NET20DC USB Debug Device". >> >> Now I want to use this device for debug purpose. But I get with >> different mainboards the same build error messages. >> >> Can anybody help? > This code hasn't be

Re: [coreboot] [PATCH] cleanup CAR code

Signed-off-by: Stefan Reinauer Index: src/cpu/intel/model_6ex/cache_as_ram.inc === --- src/cpu/intel/model_6ex/cache_as_ram.inc(revision 5682) +++ src/cpu/intel/model_6ex/cache_as_ram.inc(working copy) @@ -176,21 +176,6

[coreboot] [PATCH] cleanup CAR code

See patch - Drop lots of dead code from the various cache_as_ram.inc files. - Use some descriptive macros instead of magic numbers for MTRR MSRs - slightly reformatting code and comments Signed-off-by: Stefan Reinauer Index: src/cpu/intel/model_6ex/cache_as_ram.inc

Re: [coreboot] [PATCH] drop CONFIG_USE_PRINTK_IN_CAR and CONFIG_USE_INIT

On 8/2/10 2:59 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >> Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any >> user / >> board porter: printk should always be available in CAR mode. >> >> Also drop CONFIG_USE_INIT, it's

Re: [coreboot] [commit] r5680 - in trunk/src: northbridge/intel/i82830 northbridge/via/cn400 northbridge/via/cn700 northbridge/via/cx700 northbridge/via/vt8623 northbridge/via/vx800 southbridge/amd/cs

On 8/2/10 5:14 PM, repository service wrote: > Author: myles > Date: Mon Aug 2 17:14:13 2010 > New Revision: 5680 > URL: https://tracker.coreboot.org/trac/coreboot/changeset/5680 > > Log: > Build VGA code conditionally to avoid errors when using SeaBIOS. > > Signed-off-by: Myles Watson > Acked-b

Re: [coreboot] ASUS M4A77TD-PRO. No boot, nothing on the serial port. I'm quite lost.

On 02.08.2010, at 12:43, xdrudis wrote: > On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote: >>> When I boot with the propietary BIOS I can get GRUB2 and linux console >>> on the serial port, but only at 38400 bps. 118000 does not work. So >>> I've put 38400 in kconfig too. >> >> >>

[coreboot] [PATCH] drop CONFIG_USE_PRINTK_IN_CAR and CONFIG_USE_INIT

is one usage of CONFIG_USE_INIT which was always off in src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with those few lines. Signed-off-by: Stefan Reinauer Index: src/Kconfig === --- src/Kconfig (revision 5677)

Re: [coreboot] coreboot halts at "doing early_mtrr"

Original Message Subject:Re: [coreboot] coreboot halts at "doing early_mtrr" Date: Sun, 01 Aug 2010 17:28:41 +0200 From: Stefan Reinauer Organization: coresystems GmbH To: Corey Osgood On 8/1/10 5:10 AM, Corey Osgood wrote: > Clarify a comm

Re: [coreboot] linker problem after menuconfig

On 8/1/10 7:13 AM, austi...@msu.edu wrote: > Hi. > The wiki page for seabios recommends configuring coreboot with > CONFIG_VGA_BRIDGE_SETUP enabled and CONFIG_VGA_ROM_RUN disabled. > > When building for the jetway j7f24 target, setting those two options > in menuconfig results in the following err

Re: [coreboot] What is the rule of the SPD address assignment if there are more that 8 dimm slots?

On 7/31/10 4:56 PM, Zheng Bao wrote: > The board tht I am working on has 2 process. Each of them has 6 DIMM > slots. If you > plug 1 dimm into each slot, the SPD address will be, > Channel PCB > > P0: > DIMMA0 50h > DIMMA1 51h > DIMMA2 52h > DIMMB0 53h > DIMMB1 54h > DIMMB2 55h >

Re: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965

is nice, got no comparison though. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinaue

Re: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965

o enable MCHBAR access are ignored, all other > functions work > > Untested: > D410/D525/N400: should be the same northbridge > > Signed-off-by: Corey Osgood > Great! Got to try this on my Pineview ref board. Acked-by: Stefan Reinauer Stefan -- coresystems GmbH • Br

[coreboot] [PATCH] fix potential smm security hole

This patch resulted from a security review of coreboot's SMM handler. Feedback appreciated. Regards, Stefan - fix SMM code relocation race - make SMM relocation debugging Kconfig accessible Signed-off-by: Stefan Reinauer Index: src/southbridge/intel/i82801dx/i82801dx_

Re: [coreboot] Broken include paths

On 7/26/10 9:28 PM, Myles Watson wrote: > I was thinking of some of the ACPI code, that is not > mainboard-dependent but chipset-dependent. That's been slowly moving > to the chipset directories. > If we can get rid of exceptions by cleaning more code up in this way we should certainly do it. St

Re: [coreboot] Roda RK886EX troubles

On 7/20/10 8:17 AM, Vitaly Chertovskih wrote: > Hi! > > I'm experiencing some troubles in installing coreboot on Roda RK886EX. > Please, help me. > > Is there some manual about installation coreboot on Roda? > > I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS > image (I down

Re: [coreboot] Necessary information for supporting chipsets

On 7/12/10 10:47 AM, Takuo Fukunaga wrote: > Hi, my apologies in advance for the newbie question. > > I would just like to know what information is necessary to > support recent Intel chipsets such as Nehalem chipsets. > > Datasheets for these chipsets are available on Intel's > web site and I thi

Re: [coreboot] [PATCH] fix normal vs. fallback

On 7/9/10 8:35 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >> 1. Should Fallback always ignore CMOS? I think it would make more sense >> if Normal and Fallback were the same and both would write a decent set >> of CMOS defaults in the case of a bad checksum. > NAK if

[coreboot] [patch] libpayload standard headers

See patch become more standard with libpayload headers. PATH_MAX belongs in limits.h, tiny curses can use standard includes now. Signed-off-by: Stefan Reinauer Index: include/limits.h === --- include/limits.h(revision 0

Re: [coreboot] [PATCH] fix normal vs. fallback

On 7/9/10 6:01 PM, Myles Watson wrote: > On Fri, Jul 9, 2010 at 9:55 AM, Stefan Reinauer > wrote: >> On 7/9/10 3:36 PM, Myles Watson wrote: >>> On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: >>>> Stefan Reinauer wrote: >>>>> Even though the

Re: [coreboot] [PATCH] fix normal vs. fallback

On 7/9/10 3:36 PM, Myles Watson wrote: > On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: >> Stefan Reinauer wrote: >>> Even though the normal/fallback mechanism uses CMOS, it does not >>> require an option table. >>> Are there advantages in changing this

Re: [coreboot] [PATCH] fix normal vs. fallback

On 7/8/10 8:09 PM, Myles Watson wrote: > On Thu, Jul 8, 2010 at 11:56 AM, Patrick Georgi > wrote: >> Am 08.07.2010 19:50, schrieb Myles Watson: >>> BOOTBLOCK_NORMAL allows the user to use CMOS values to select which >>> image to boot. This patch: >>> >>> - makes BOOTBLOCK_NORMAL depend on USE_O

Re: [coreboot] PATCH: Fix CMOS Tables support for all boards.

On 7/7/10 8:28 PM, Myles Watson wrote: > On Wed, Jul 7, 2010 at 8:24 AM, Myles Watson wrote: >>> Rev 5653. >>> >>> Thanks, >>> Myles >>> >>> Not sure why there were no errors, but: >>> >>> 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No >>> such file or directory >> That

[coreboot] [PATCH] warnings -> errors

Hi, I suggest applying the following patch to encourage folks to get their warnings fixed and cleaned up. Stefan Signed-off-by: Stefan Reinauer Index: src/Kconfig === --- src/Kconfig (revision 5655) +++ src/Kconfig (working copy

Re: [coreboot] [PATCH] warnings

On 7/7/10 4:56 PM, Myles Watson wrote: > Kill a few more warnings. > > Signed-off-by: Myles Watson > > Thanks, > Myles > Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email

Re: [coreboot] Position Independent Code

ergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Position Independent Code

On 7/7/10 1:04 PM, ali hagigat wrote: > Is Coreboot source code is a position independent code? I mean, will > it be executed from any arbitrary location of the main memory? Most of it, no. > > Can it be revoked and correctly executed by a bootloader like Grub if > I make a binary image of it a

Re: [coreboot] PATCH: Fix CMOS Tables support for all boards.

On 7/6/10 11:05 PM, Myles Watson wrote: > On Wed, Jun 30, 2010 at 11:52 AM, Edwin Beasant > wrote: >> Seems best of all worlds to me :-) >> Can we get an ack and a commit? > Rev 5653. > > Thanks, > Myles > Not sure why there were no errors, but: 9 src/include/pc80/mc146818rtc.h:89:26: warn

Re: [coreboot] 3 questions about coreboot

On 7/7/10 12:44 PM, ali hagigat wrote: > Stefan, > > BIOS chip is not connected to CPU directly after reset!! It's never connected directly, anyways, but through some kind of bridge. Usually the southbridge. > > I mean the hardware immediately accesses BIOS chip after reset > but at >

Re: [coreboot] 3 questions about coreboot

On 7/7/10 6:42 AM, ali hagigat wrote: > My chipset is Intel Core2Due/945/ICH7. > > I have 3 questions. > > First question: > I wonder how PCI memory read cycles can read an instruction from > F000:FFF0 right after reset which is the first instruction of BIOS. x86 CPUs are designed like that. Go re

Re: [coreboot] [PATCH] superiotool: libsuperiodetect

On 6/30/10 4:16 PM, Carl-Daniel Hailfinger wrote: >> 15kb lzma compressed is nothing. >> >> > 8 kB more or less in a recovery payload of a coreboot image are not > negligible IMHO. > > In normal OS environments people don't use compressed binaries, and > there a 2 MB size increase for flash

Re: [coreboot] [PATCH] superiotool: libsuperiodetect

t; +#endif /* LIBSUPERIODETECT */ > }; > hm ... the comment is very terse. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Error creating thumbnail: libgomp: Thread creation failed: Resource temporarily unavailable

coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: cor

Re: [coreboot] [PATCH]libpayload: more libc support

robably some file is missing an svn add? With the issue fixed, Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]libpayload: add defines to lpgcc

r __powerpc__ already set by the compiler? Anyways, Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR

On 6/21/10 7:24 PM, Joseph Smith wrote: >>> Why print out a "generic" message? >>> >> I think it just means "not-stepping-specific" >> >> > I like your verbage alot better than "generic". > Or even "default" would be better than "generic". > > So, any native speakers with a good sug

Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR

On 6/21/10 12:15 PM, Joseph Smith wrote: > > > On Mon, 21 Jun 2010 11:48:33 +0200, Peter Stuge wrote: > >> Joseph Smith wrote: >> > Before I did not get the "Using generic cpu ops (good)" is that ok? > The message seems to suggest so.. >>> Hmm, to me i

Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR

On 20.06.2010, at 14:44, Joseph Smith wrote: On 06/20/2010 07:46 AM, Stefan Reinauer wrote: On 6/20/10 10:04 AM, Joseph Smith wrote: Hello, This patch adds a new socket for FCPGA370 and PGA370 CPU's. This new socket (called socket_FC_PGA370) will make the CAR transition alot easier.

Re: [coreboot] [PATCH] Support for Intel D810E2CB (i810e/ICH2)

> Signed-off by: Joseph Smith Acked-by: Stefan Reinauer with some caveats: > Index: src/mainboard/intel/d810e2cb/gpio.c > === > --- src/mainboard/intel/d810e2cb/gpio.c (revision 0) > +++ src/mainboard/

Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR

sted. > > Signed-off by: Joseph Smith with two caveats: Acked-by: Stefan Reinauer > Index: src/cpu/intel/Kconfig > === > --- src/cpu/intel/Kconfig (revision 5634) > +++ src/cpu/intel/Kconfig (working copy)

Re: [coreboot] [PATCH] i810 GFXUMA and Northbridge fixes

* 1024); > + printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10); > + } > You might want to read the SMRAM register intead of relying on the setting of the config variable in case an invalid value sneaked in. Other than that: Acked-by: Stefan Reinaue

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