Re: [coreboot] [RFH] Sponsor for Lenovo X60 wanted

Hi Paul, Paul Menzel paulepan...@users.sourceforge.net writes: in the last weeks I started working a little on the Lenovo X60 support [1]. There are several issues like non-working 3D support with Linux 3.12+ [2]. Also Linux 3.11+ (or earlier) is unable to initialize the graphics device

Re: [coreboot] ThinkPad T60p coreboot config file

Hi Thom, I have a ThinkPad T60p 2007-CTO. Does anyone know the flash chip used and have a known working config file ? I know this model has been successfully flashed. Don't want to have to disassemble my laptop. That disassembly is required to identify the flash chip is going to slow coreboot

Re: [coreboot] T60: Beeping for the battery states

Hi Paul, Paul Menzel paulepan...@users.sourceforge.net writes: the proprietary BIOS allows to disable/mute sound, when battery status is low or the power cable is plugged in or out. Is it possible to configure that with coreboot or ectool [1]? src/ec/lenovo/h8 $ tail -9 h8.h

Re: [coreboot] 486 Motherboard from scratch

Hi Rex, Rex O'Regan rexorega...@yahoo.com.au writes: How hard would it be to design, source components and construct a motherboard for something simple such as a 486DX from scratch? I am interested in doing this primarily to learn about what it takes to design a motherboard and what's in

Re: [coreboot] New patch to review for coreboot: 36c6cc6 SMBIOS: Add Type 38 (IPMI) data structure

ron minnich rminn...@gmail.com writes: was there some platform on which IPMI was essential to bringup? It's really not that great to have otherwise. I'm currently porting coreboot to a Fujitsu-Siemens TX200S3 server. The mainboard has a BMC on it. This BMC has a additional watchdog besides the

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60

Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net writes: [CC coreboot@coreboot.org] Am 01.07.2012 16:45 schrieb Henrique de Moraes Holschuh: On Mon, 25 Jun 2012, Carl-Daniel Hailfinger wrote: You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot? How would that

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60

it would be very welcome (e.g. which T60 are supported or at least expected to work? AFAIK all T60/X60 variants work with coreboot. Sven Schnelle knows more, he is the one who ported coreboot to those thinkpads. I have the following thinkpad models running on coreboot: Thinkpad X60s (Model 1702

[coreboot] RFC: automatic mptable creation

Hi coreboot folks, i've just pushed the following changes for discussion: http://review.coreboot.org/#/c/1137/ http://review.coreboot.org/#/c/1138/ Those changes add support for creating the MPTABLE during runtime, which resolves one of the most painful tasks in the past during porting a new

Re: [coreboot] bluetooth on Thinkpad X60s

Hi, Motiejus Jakštys desired@gmail.com writes: On Tue, May 1, 2012 at 8:27 PM, Patrick Georgi patr...@georgi-clan.de wrote: Am Di 01 Mai 2012 21:24:00 CEST schrieb Motiejus Jakštys: 2) The only way to disable bluetooth device now is modifying coreboot source code. There should be a

Re: [coreboot] How to port core boot

On 02/07/2012 04:21 PM, ali hagigat wrote: This time i do ram_check between 1M to 3M, here is the serial port output: coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 18:39:18 IRST 2012 starting... Testing DRAM : 0010 - 0090 DRAM fill: 0x0010-0x0090 0090 DRAM filled DRAM verify:

Re: [coreboot] Lenovo T60p 8742 Y19 - Black screen

Hi Matias, On 10/27/2011 01:12 AM, Matias Jose Seco wrote: currently i'm trying to boot my laptop over the newly flashed bios with coreboot, but actually, despite power button, leds and cd player working properly i dont get any response from the display. you can download the coreboot Image

[coreboot] [RFC] (ab)using the devicetree/device drivers for automatic SMBIOS table generation

Hi List, with commit 164bcfdd1b0b2cc789203eeb9e3ff842df215a7c (Add automatic SMBIOS table generation) i've introduced a new member '(*get_smbios_data) in struct device_operations / struct chip_operations. We might use that now to generate SMBIOS tables based on device drivers. I've just

Re: [coreboot] TPM support for SeaBIOS -- looking for a tester on real hardware

Hi Stefan, Stefan Berger stef...@linux.vnet.ibm.com writes: Would anybody be interested in testing the TPM support I added to SeaBIOS. I unfortunately don't have a motherboard myself where I could try it. I have added the support to SeaBIOS for the TPM device model in Qemu. What you would

Re: [coreboot] TPM support for SeaBIOS -- looking for a tester on real hardware

Hi Stefan, Stefan Berger stef...@linux.vnet.ibm.com writes: On 09/08/2011 02:47 AM, Sven Schnelle wrote: Stefan Bergerstef...@linux.vnet.ibm.com writes: Would anybody be interested in testing the TPM support I added to SeaBIOS. I unfortunately don't have a motherboard myself where I

Re: [coreboot] Coreboot on the Thinkpad T61p ?

Hi Patrick, Patrick Arnoux parn...@adelphia.net writes: On 07/16/11 01:55 PM, Peter Stuge wrote: Patrick Arnoux wrote: we don't have any documentation for the i965 (crestline) Memory Controller Not sure if this is the relevant document, .. Mobile Intel® 965 Express Chipset Family

Re: [coreboot] Coreboot on the Thinkpad T61p ?

Thom Lauret diracsh...@gmail.com writes: Has anyone succeeded installing coreboot onto a Lenovo Thinkpad T61/p ? I see it has been achieved on a T60. Unfortunaterly that won't work, as we don't have any documentation for the i965 (crestline) Memory Controller used in that Notebook. Regards,

[coreboot] caching in SMI handler

Hi List, i've encountered an interesting problem on my Thinkpad T60: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how

[coreboot] [PATCH] SMM: add defines for APM_CNT register

in the current code, the defines for the APM_CNT (0xb2) register are duplicated in almost every place where it is used. define those values in cpu/x86/smm.h, and only include this file. And while at it, fixup whitespace. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/include/cpu/x86

[coreboot] [PATCH] i82801gx: enable ACPI during S3 resume

disabling ACPI during S3 wakeup breaks ACPI wakeup, as the Host OS is assuming that ACPI is enabled. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/southbridge/intel/i82801gx/lpc.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel

Re: [coreboot] [PATCH 1/2] SMM: add mainboard_apm_cnt() callback

Stefan Reinauer stefan.reina...@coreboot.org writes: --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -362,6 +362,9 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the

[coreboot] [PATCH 1/2] SMM: add mainboard_apm_cnt() callback

motherboards can use this hook to get notified if someone writes to the APM_CNT port (0xb2). If the hook returns 1, the chipset specific hook is also skipped. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/include/cpu/x86/smm.h |2 +- src/southbridge/intel

[coreboot] [PATCH 2/2] X60: add support for handling EC events in SMM

register space, we're using 0x62/0x66 as EC I/O ports as long as ACPI is disabled. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/devicetree.cb |4 +- src/mainboard/lenovo/x60/mainboard_smi.c | 89 +- 2 files changed, 90 insertions(+), 3

Re: [coreboot] Keyboard not working on Thinkpad X60/T60

Hi Kevin, Kevin O'Connor ke...@koconnor.net writes: On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote: Kevin O'Connor ke...@koconnor.net writes: Some ps2 ports send NAK (0xfe) when there is no keyboard plugged in. The detection for NAK was added so that it doesn't take a full

Re: [coreboot] Lenovo T60 coreboot build error

Josh Stump josh+coreb...@pcinw.net writes: Thank you kindly.  I have now compiled the BIOS.  Next challenge is how to get flashrom to flash it.  The wiki shows flashrom support.  I have downloaded the latest svn version and flashrom does not detect my system.  flashrom -L does not list Lenovo

Re: [coreboot] Hackaton in Prague 2011

Rudolf Marek r.ma...@assembler.cz writes: I think it is time to make a reservation for the Hotel/Hostel. Is there anyone else besides Peter, Sven and Florentin? Just reminding that it take place in Prague on last weekend in May. Cool! Thanks for organizing this Event! The Hackaton topics I

Re: [coreboot] Keyboard not working on Thinkpad X60/T60

Kevin O'Connor ke...@koconnor.net writes: On Wed, May 04, 2011 at 10:16:17AM +0200, Sven Schnelle wrote: Will do. But right now i have the problem that the Keyboard isn't working on cold boot - seabios is probably started so early that some hardware parts are not finished with reset

[coreboot] Keyboard not working on Thinkpad X60/T60 (was: Re: [commit] r6554 - trunk/src/cpu/intel/model_6ex)

Hi Setfan, Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110503 21:41]: Stefan Reinauer stefan.reina...@coreboot.org writes: Can you do a new analysis on where the boot time goes now? It would be nice to see if there are more optimizations we

Re: [coreboot] Keyboard not working on Thinkpad X60/T60

Sven Schnelle sv...@stackframe.org writes: Hi Setfan, Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110503 21:41]: Stefan Reinauer stefan.reina...@coreboot.org writes: Can you do a new analysis on where the boot time goes now? It would

Re: [coreboot] [PATCH] Add option 'compress ramstage'

Hi Stefan, hi Eric, Stefan Reinauer stefan.reina...@coreboot.org writes: * Eric W. Biederman ebied...@xmission.com [110503 01:26]: Was that a destination hard code? The code itself should come out of the last couple of megabytes before 4G. Yes. Only the lower 1MB of the destination

Re: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex

Hi Paul, Paul Menzel paulepan...@users.sourceforge.net writes: Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service: Author: svens Date: Tue May 3 09:55:43 2011 New Revision: 6554 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554 Log: Enable caching for ROM

Re: [coreboot] [commit] r6553 - trunk/src/southbridge/intel/i82801gx

Peter Stuge pe...@stuge.se writes: repository service wrote: +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue May 3 09:55:30 2011(r6553) @@ -38,5 +38,10 @@ int default 1 +config BOOTBLOCK_SOUTHBRIDGE_INIT +string +default

Re: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex

Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110503 10:23]: Hi Paul, Paul Menzel paulepan...@users.sourceforge.net writes: Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service: Author: svens Date: Tue May 3 09:55:43 2011

[coreboot] [PATCH] Add option 'compress ramstage'

, which are really slow on SPI buses. So give the user the option to store ramstage uncompressed, if he has enough memory. Signed-off-by: Sven Schnelle sv...@stackframe.org --- Makefile.inc |4 src/Kconfig |8 2 files changed, 12 insertions(+), 0 deletions(-) diff --git

Re: [coreboot] [commit] r6550 - in trunk: . conf db db/revpropsdb/revprops/0 db/revs db/revs/0 db/transactionsdb/txn-protorevs hooks locks

Scott Duplichan sc...@notabs.org writes: Sorry about that commit. I am trying to make a local svn so that I can incrementally apply a large change set and end up with a series of patches instead of one huge patch. Executing TortoiseSVN import on my local machine wrote to the remote

[coreboot] [PATCH] Enable Ultrabay and IDE interface if Ultrabay device is present

this small patch series enable the Ultrabay found in T60 and X60 Laptops. The X60 is a bit more ugly as the T60 because the X60 ultrabase notifies the system over some GPIO Lines about Ultrabay state, while the T60 uses PMH7 and the EC for status information. I'm not sure if everyone likes

[coreboot] [PATCH 2/4] Lenovo PMH7: add pmh7_ultrabay_power_enable()

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/pmh7/pmh7.c |8 src/ec/lenovo/pmh7/pmh7.h |1 + 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index d536d74..276a378 100644 --- a/src/ec

[coreboot] [PATCH 3/4] T60: enable Ultrabay if device is plugged in

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/t60/devicetree.cb |2 +- src/mainboard/lenovo/t60/mainboard.c | 13 - 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60

[coreboot] [PATCH 4/4] X60: enable Ultrabay if device is plugged in

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/Makefile.inc |1 + src/mainboard/lenovo/x60/devicetree.cb |2 +- src/mainboard/lenovo/x60/dock.c|6 +- src/mainboard/lenovo/x60/dock.h|1 + src/mainboard/lenovo/x60/mainboard.c

[coreboot] [PATCH 1/4] Lenovo H8: add h8_ultrabay_device_present()

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/h8/h8.c |6 ++ src/ec/lenovo/h8/h8.h |5 + 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 6a59525..fafaef2 100644 --- a/src/ec/lenovo/h8/h8.c

Re: [coreboot] [PATCH 3/4] pci1x2x: use pci_ops set_subsystem instead of custom code

Hi Stefan, Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110419 21:47]: Signed-off-by: Sven Schnelle sv...@stackframe.org Will that also need a change in the nokia IP530 board's devicetree.cb? Of course. Added the neccessary subsystemid statement

[coreboot] [PATCH 4/4] pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/southbridge/ti/pci1x2x/pci1x2x.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index a3ec35c..bc4ee89 100644 --- a/src/southbridge

[coreboot] [PATCH 1/4] pci1x2x: use devicetree register configuration

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/nokia/ip530/Kconfig | 25 - src/mainboard/nokia/ip530/devicetree.cb |9 +++ src/southbridge/ti/pci1x2x/pci1x2x.c| 36 +- 3 files changed, 25 insertions(+), 45

[coreboot] [PATCH 2/4] pci1x2x: add PCI1510 device IDs

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/include/device/pci_ids.h |1 + src/southbridge/ti/pci1x2x/pci1x2x.c |6 ++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6286cd6

[coreboot] [PATCH] southbridge/ti/pci1x2x cleanup

Hi List, this patch series is a generic cleanup of the pci1x2x driver. Basically it does: - move register config from Kconfig to devicetree.cb - use the generic pci/cardbus functions - add proper subsystemid configuration - remove latency. cacheline size, bridge control register settings, as

[coreboot] [PATCH 3/4] pci1x2x: use pci_ops set_subsystem instead of custom code

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/southbridge/ti/pci1x2x/pci1x2x.c | 25 ++--- 1 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 0628f1f..a3ec35c 100644

Re: [coreboot] [PATCH] add ThinkPad T60

Hi Stefan, Stefan Reinauer stefan.reina...@coreboot.org writes: On 4/17/11 6:07 AM, Sven Schnelle wrote: Index: t60/Kconfig === --- t60/Kconfig (revision 6509) +++ t60/Kconfig (working copy) @@ -56,4

[coreboot] [PATCH] add ThinkPad T60

Hi List, the attached patch adds support for the ThinkPad T60 to coreboot. it is diffed against the existing X60 port. Signed-off-by: Sven Schnelle sv...@stackframe.org Index: Kconfig === --- Kconfig (revision 6509) +++ Kconfig

Re: [coreboot] [PATCH 1/2] EC: Add Lenovo H8

Stefan Reinauer stefan.reina...@coreboot.org writes: diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu new file mode 100644 index 000..d9275b5 --- /dev/null +++ b/src/mainboard/emulation/qemu ... +#include southbridge/intel/i82801gx/nvs.h ... +

[coreboot] [PATCH 2/2] PMH7: Add chip config

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/pmh7/chip.h |9 + src/ec/lenovo/pmh7/pmh7.c | 12 src/ec/lenovo/pmh7/pmh7.h |1 + src/mainboard/lenovo/x60/devicetree.cb |1 + src/mainboard/lenovo/x60

[coreboot] [PATCH 1/2] EC: Add Lenovo H8

-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/Kconfig |1 + src/ec/lenovo/Makefile.inc |1 + src/ec/lenovo/h8/Kconfig |3 + src/ec/lenovo/h8/Makefile.inc |1 + src/ec/lenovo/h8/acpi/ac.asl

[coreboot] [PATCH 2/2] PMH7: Add chip config

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/pmh7/chip.h |9 + src/ec/lenovo/pmh7/pmh7.c |4 src/mainboard/lenovo/x60/devicetree.cb |1 + src/mainboard/lenovo/x60/mainboard.c |2 -- 4 files changed, 14 insertions

[coreboot] [PATCH 2/2] PMH7: Add chip config

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/lenovo/pmh7/chip.h |9 + src/ec/lenovo/pmh7/pmh7.c |4 src/mainboard/lenovo/x60/devicetree.cb |1 + src/mainboard/lenovo/x60/mainboard.c |7 --- 4 files changed, 14 insertions

[coreboot] [PATCH] i945: improve get_top_of_ram()

The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/northbridge/intel/i945

Re: [coreboot] [commit] r6478 - trunk/src/mainboard/lenovo/x60

Hi Stefan, Stefan Reinauer stefan.reina...@coreboot.org writes: Sven, could you put this in a separate function called by mainboard enable? e.g. print_ec_version() or some such. Good idea. Committed as r6480. Thanks, Sven. -- coreboot mailing list: coreboot@coreboot.org

[coreboot] [PATCH] ICH7: Fix register naming error

usable here. Als adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/getac/p470/acpi/ec.asl | 26 +++--- src/southbridge/intel/i82801gx/acpi/ich7.asl | 46 ++--- 2

[coreboot] [PATCH 1/2] Add GPIO definitions to PC87392 superio

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/superio/nsc/pc87392/pc87392.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h index 759f109..4756351 100644 --- a/src/superio/nsc

[coreboot] X60: add support for Ultrabase X6

Hi List, these patches add support for the Ultrabase X6 to the Lenovo X60 port. while we already did initialize a Docking station in romstage to have serial output, these patches move those code to dock.c, which is used in romstage and SMM for Docking/Undocking. This patch only adds the basic

[coreboot] [PATCH 2/2] X60: add dock code

Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/Makefile.inc|3 +- src/mainboard/lenovo/x60/acpi/ec.asl |6 + src/mainboard/lenovo/x60/acpi/gpe.asl

[coreboot] [RFC] Build system changes

Hi List, This patch series contains two patches. The first fixes building coreboot with multiple jobs (The -jX option in make). When building coreboot without a build/ directory, the coreboot.pre target fails to build, as build/config.h doesn't exist at that stage. The second patch is rather

[coreboot] [PATCH 1/2] BUILD: add config.h dependency

Signed-off-by: Sven Schnelle sv...@stackframe.org --- Makefile.inc |2 +- src/arch/x86/Makefile.inc |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 54d472a..3f553c6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -61,7

Re: [coreboot] DRAM self refresh check in src/northbridge/i945/raminit.c

Hi Stefan, Stefan Reinauer stefan.reina...@coreboot.org writes: one of the last remaining problems with the ThinkPad X60 port is that coreboot does a full reset on ACPI S3 wakeup. There's an explicit check that the DRAM self refresh bits in PMSTS (MCHBAR offset 0xf14) are set. For (yet)

[coreboot] DRAM self refresh check in src/northbridge/i945/raminit.c

Hi List, one of the last remaining problems with the ThinkPad X60 port is that coreboot does a full reset on ACPI S3 wakeup. There's an explicit check that the DRAM self refresh bits in PMSTS (MCHBAR offset 0xf14) are set. For (yet) unknown reasons, those bits are not set on my Thinkpad after

[coreboot] [PATCH] BUILD: add -MMD to iasl cpp call

Right now there are no dependency rules for compiling dsdt.asl. If ACPI code includes asl files, the dsdt isn't recompiled if any of those file is changed. Add the flags to the preprocessor call to have it generate the neccessary dependency rule. Signed-off-by: Sven Schnelle sv...@stackframe.org

[coreboot] [PATCH 1/2] ACPI EC: add ec_query function

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/acpi/ec.c |6 ++ src/ec/acpi/ec.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 1d4ffb8..2680aa3 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -116,6

[coreboot] [PATCH] X60: remove beep call from _Q26/_Q27

no need to trigger sound, the EC takes care of generating the annoying AC state beep if enabled in the sound mask. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/acpi/ec.asl |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mainboard

[coreboot] [PATCH] X60: Add notifications for LID objects

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/acpi/ec.asl | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 7e2b94d..2318817 100644 --- a/src

[coreboot] [PATCH] X60: Add _PRW/_PSW methods to LID/SLPB objects

This patch adds the required methods for enabling/disabling the LID and SLPB objects as wake source. On Thinkpads, the Fn key can (and is by the Vendor BIOS) programmed as Wake source, so let's do it the same way. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60

Re: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI accesses

Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110312 01:18]: Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/mainboard.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mainboard

Re: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI accesses

Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110312 01:18]: Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/mainboard.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mainboard

Re: [coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair configurable

Stefan Reinauer stefan.reina...@coreboot.org writes: * Sven Schnelle sv...@stackframe.org [110312 01:18]: Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/acpi/ec.c | 23 --- src/ec/acpi/ec.h |1 + 2 files changed, 17 insertions(+), 7 deletions(-) I

[coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair configurable

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/acpi/ec.c | 23 --- src/ec/acpi/ec.h |1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index e353260..1d4ffb8 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec

[coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI accesses

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/mainboard.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index b8e6a49..79e4a83 100644 --- a/src/mainboard

[coreboot] [PATCH 1/3] ACPI EC: add ec_set_bit() / ec_clr_bit()

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/ec/acpi/ec.c | 10 ++ src/ec/acpi/ec.h |2 ++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 7a01b7e..e353260 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c

[coreboot] RFC: Make ec/acpi ports configurable

', as this describes better what it does. Regards, Sven. From 9a3d656d19849bf842b0f2e1e3a86ee6b0d5a77a Mon Sep 17 00:00:00 2001 From: Sven Schnelle sv...@stackframe.org Date: Tue, 8 Mar 2011 16:43:28 +0100 Subject: [PATCH] ec/acpi: make ACPI register pair configurable To: coreboot@coreboot.org Cc: sv

[coreboot] [PATCH] X60: add thermal zone 0

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/acpi/ec.asl |4 +++- src/mainboard/lenovo/x60/acpi/thermal.asl | 26 ++ 2 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src

[coreboot] [PATCH] X60: add thermal zone 1

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/lenovo/x60/acpi/thermal.asl | 15 +++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl index b7256ce..35b6f14

Re: [coreboot] [PATCH] add PC87384 SuperIO

Peter Stuge pe...@stuge.se writes: Sven Schnelle wrote: Signed-off-by: Sven Schnelle sv...@stackframe.org Acked-by: Peter Stuge pe...@stuge.se r6427. Thanks, Sven. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

Hi Keith, Keith Hui buu...@gmail.com writes: Option C with GPLv2+ licensing. A few quick things: SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name. I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and

[coreboot] [PATCH] add PC87384 SuperIO

Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/superio/nsc/Kconfig |2 + src/superio/nsc/Makefile.inc |1 + src/superio/nsc/pc87384/Makefile.inc | 22 + src/superio/nsc/pc87384/chip.h | 31 + src/superio/nsc/pc87384/pc87384.h

[coreboot] (no subject)

Hi List, this patches are adding a new subsystemid option to sconfig. This option can be used to specify subsystem IDs in devicetree.cb, and is intended to replace the old Kconfig option. Main motivation for this patch is the fact that the current Kconfig mechanism only allows to set a Subsystem

[coreboot] [PATCH 1/2] Add subsystemid option to sconfig

in the following example: device pci 00.0 on subsystemid dead beef inherit end If the user don't want to inherit a Subsystem for a single device, he can specify 'subsystemid 0 0' on this particular device. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src

[coreboot] [PATCH v2] new subsystemid option for scnfig

Hi List, i fixed a few boards which missed the proper Kconfig/sconfig conversion. Thanks to Peter Stuge for pointing that out. Also fix a few white space errors. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 1/2] Add subsystemid option to sconfig

in the following example: device pci 00.0 on subsystemid dead beef inherit end If the user don't want to inherit a Subsystem for a single device, he can specify 'subsystemid 0 0' on this particular device. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src

Re: [coreboot] [PATCH 1/2] Add subsystemid option to sconfig

Peter Stuge pe...@stuge.se writes: Sven Schnelle wrote: Allow user to add 'subsystemid vendor device [inherit]' to devicetree.cb for PCI and PCI domain devices. Example: device pci 00.0 on subsystemid dead beef end If the user wants to have this ID inherited

Re: [coreboot] [PATCH 2/2] Use subsystem id from devicetree.cb instead of Kconfig and move all boards to the new config scheme.

Peter Stuge pe...@stuge.se writes: Sven Schnelle wrote: 158 files changed, 120 insertions(+), 561 deletions(-) Signed-off-by and commit message is missing. But: Acked-by: Peter Stuge pe...@stuge.se r6421, thanks. ~sven -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [commit] r6420 - in trunk: src/include/device util/sconfig

Stefan Reinauer stefan.reina...@coreboot.org writes: * repository service s...@coreboot.org [110301 20:58]: Author: svens Date: Tue Mar 1 20:58:15 2011 New Revision: 6420 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6420 Modified: trunk/src/include/device/device.h

Re: [coreboot] [PATCH] r6420-remove-unused-var.patch

Sylvain 'ythier' Hitier sylvain.hit...@gmail.com writes: (Please keep me in CC, I'm not subscribed to the list) After reading r6420. Signed-off-by: Sylvain ythier Hitier sylvain.hit...@gmail.com Index: util/sconfig/main.c ===

Re: [coreboot] [PATCH] r6421-correct-ids.patch

Sylvain 'ythier' Hitier sylvain.hit...@gmail.com writes: (Please keep me in CC, I'm not subscribed to the list) After reading r6421. Signed-off-by: Sylvain ythier Hitier sylvain.hit...@gmail.com Index: src/mainboard/asus/m2v/devicetree.cb

[coreboot] [PATCH] add functions to set Subsystem Vendor/Device to rl5c746

Hi List, this patch adds functions to set the Subsystem Vendor/Device ID fields on Ricoh RL5C746. Signed-off-by: Sven Schnelle sv...@stackframe.org Index: src/southbridge/ricoh/rl5c476/rl5c476.c === --- src/southbridge/ricoh

Re: [coreboot] [PATCH] add functions to set Subsystem Vendor/Device to rl5c746

Peter Stuge pe...@stuge.se writes: Sven Schnelle wrote: this patch adds functions to set the Subsystem Vendor/Device ID fields on Ricoh RL5C746. Is the procedure device specific? Yes, the ricoh chip needs an additional Write enable to set the Subsystem Vendor/Device ID. ~sven -- coreboot

Re: [coreboot] [PATCH] add functions to set Subsystem Vendor/Device to rl5c746

Sven Schnelle sv...@stackframe.org writes: this patch adds functions to set the Subsystem Vendor/Device ID fields on Ricoh RL5C746. r6412. ~svens -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] add SPD address mapping to i945

Sven Schnelle sv...@stackframe.org writes: Hi Patrick, thanks for you reply. I've attached a new patch which addresses those issues. [..] r6374 in svn. Sven. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] add SPD address mapping to i945

The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to

Re: [coreboot] [PATCH] add SPD address mapping to i945

to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle sv...@stackframe.org --- src/mainboard/getac/p470

[coreboot] [PATCH] X60: enable SMI handler

Hi List, this patch enables SMI Support for the Thinkpad X60. Signed-off-by: Sven Schnelle sv...@stackframe.org Index: src/mainboard/lenovo/x60/Kconfig === --- src/mainboard/lenovo/x60/Kconfig (revision 6365) +++ src/mainboard

[coreboot] [PATCH] X60: Add basic ACPI files

tables. Signed-off-by: Sven Schnelle sv...@stackframe.org Index: src/mainboard/lenovo/x60/Kconfig === --- src/mainboard/lenovo/x60/Kconfig (revision 6364) +++ src/mainboard/lenovo/x60/Kconfig (working copy) @@ -20,7 +20,7 @@ select GFXUMA

[coreboot] [PATCH v4] Lenovo X60s support

=== --- src/mainboard/lenovo/x60s/devicetree.cb (revision 6326) +++ src/mainboard/lenovo/x60s/devicetree.cb (working copy) @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle sv...@stackframe.org

Re: [coreboot] Fwd: inteltool: first preview for machine-readable output

Hi, Антон Кочков anton.koch...@gmail.com writes: At first, can you please give us a few use cases for this patch? inteltool: first preview for machine-readable output Signed-off-by: Anton Kochkov anton.koch...@gmail.com --- This is only for preview and discussion, it's still ugly and dont

Re: [coreboot] [PATCH] add PC87382 to superiotool

Uwe Hermann u...@hermann-uwe.de writes: Thanks, committed as r6327 with minor whitespace and consistency changes. +{0xf4, PC87382, { +{ NOLDN, NULL, +{ 0x20, 0x21, 0x22, 0x26, 0x27, 0x29, EOT }, +{ 0xf2, 0x11, 0x63, 0x00, 0x00, 0x00,

[coreboot] [PATCH] add PC87382 to superiotool

this address pair. Signed-off-by: Sven Schnelle sv...@stackframe.org diff --git a/util/superiotool/nsc.c b/util/superiotool/nsc.c index 982a01d..5909844 100644 --- a/util/superiotool/nsc.c +++ b/util/superiotool/nsc.c @@ -306,6 +306,23 @@ static const struct superio_registers reg_table

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