Hello fellow Coreboot enthusiasts,
I am not sure if I am the only one annoyed/confused when I see coreboot
messages like "Error reading from Cr50" or "Did not recognize Cr50 version
format", etc. while the device in fact is using a different GSC (Google
Security Chip).
Before I go for it - would
Julius,
why can't you use the gerrit 'download' button to either cherry pick the
patch or pull the stack?
-vb
On Tue, May 25, 2021 at 5:14 PM Julius Werner wrote:
> Hi Patrick, Martin,
>
> I just noticed that we seem to have dropped support for cgit on the
> coreboot Gerrit. I don't exactly r
On Tue, Jun 25, 2019 at 1:29 PM Julius Werner wrote:
> The improvement of requiring a { on the ifs is known to
> > have positive impact; it's why Rust and Go both require it to my
> > understanding.
>
> How is this actually "known"?
Mandatory brackets are especially helpful when one makes quic
Why does it have to be done by Seabios as opposed to Linux? It is easy to
create a USB stick which would boot Linux compiled with permissions needed
and with startup files which will program the new firmware image. This
would be much easier to debug and modify when needed, right?
-vb
On Thu, Feb
On Fri, May 25, 2018 at 8:24 AM Patrick Georgi wrote:
> Am Fr., 25. Mai 2018 um 17:05 Uhr schrieb Vadim Bendebury <
> vben...@chromium.org>:
> > limiting width to 80 columns helps greatly when one wants to see several
> screens side by side.
>
> $ echo $COLUMNS
>
ieb Vadim Bendebury <
> vben...@chromium.org>:
> > limiting width to 80 columns helps greatly when one wants to see several
> screens side by side.
>
> $ echo $COLUMNS
> 274
>
> Two terminals of 120 + metadata (linenumbers, window frames, ...) fit well,
> and that&
limiting width to 80 columns helps greatly when one wants to see several
screens side by side. And of course implicitly keeps the code cleaner - if
so much indentation is needed, the code is likely ripe for refactoring.
I don't write much coreboot code, but I stare at it quite often ;)
-vb
On F
Speaking of coding style: there is no pre-upload check configured in the
coreboot git repo, if I am not mistaken, should one be added?
As for this particular change - I don't like wasting vertical space, but
looks like overwhelming sentiment is supporting this proposal, so I sure
can live with it,
it's just a list with an applied rs232 filter, DigiKey has tons of 3 pin
UART cables as well.
-vb
On Mon, Mar 5, 2018 at 8:22 AM, Nico Huber wrote:
> On 05.03.2018 17:06, Vadim Bendebury wrote:
> > Did you consider one of these:
> >
> > https://www.digikey.com/pr
Did you consider one of these:
https://www.digikey.com/products/en/cable-assemblies/smart-cables/468?k=ftdi+uart&k=&pkeyword=ftdi+uart&pv493=316&FV=ffe001d4&quantity=0&ColumnSort=0&page=1&pageSize=25
there are many options, it is important to match the cable's VDD to your
board's (1.8V vs 3.3V),
[+cc a couple of guys who might have some advice in this respect]
On Fri, Dec 1, 2017 at 5:07 AM, Аладышев Константин
wrote:
> Hello! I'm trying to understand, what is the easiest way today to integrate
> EC to custom motherboard? What controller should I choose for new custom
> motherboard?
>
>
with the right kernel configs the firmware log contents can be seen in
/sys/firmware/log after Linux has booted up.
-vb
On Thu, Nov 23, 2017 at 5:12 AM, ingegneriafore...@alice.it <
ingegneriafore...@alice.it> wrote:
> Thank very much guys !
>
> Please, I've understood the use of cbmem, however
the repo manifest.
--vb
On Tue, Oct 3, 2017 at 2:10 AM, Paul Kocialkowski wrote:
> Hi,
>
> Le lundi 02 octobre 2017 à 13:47 -0700, Vadim Bendebury a écrit :
> > the entry threshold is a big high, but I am sure the Chome OS EC team
> would
> > appreciate your contri
Yes, it will require user authorization, there will also be an RMA case
with its own authorization scheme.
-v
On Mon, Oct 2, 2017 at 5:16 PM, Trammell Hudson wrote:
> On Mon, Oct 02, 2017 at 05:02:40PM -0700, Vadim Bendebury wrote:
> > note that this debug header is going away in n
note that this debug header is going away in new Chrome OS designs. Its
functionality is going to be provided by the closed case debugging (aka
CCD) facility, where authorized user using a special debug cable can gain
access to the AP and EC consoles, reprogram AP and EC firmware, etc.
-vb
On Mo
Hi Paul,
I don't think there is an external mailing list for chromium OS EC
development.
To see the manifest which the repo utility requires you need to setup the
Chrome OS chroot environment first (aka cros SDK), I am not sure if you did
that, but this is a pretty expensive procedure, requiring
Wow, this is gross, Samsung screwed up again. At least the TVs don't catch
fire :)
As a side note I am pretty sure it would have been no problem returning
those TVs here in the states, gotta love consumer protection here.
-vb
On Fri, Aug 25, 2017 at 10:16 AM, ron minnich wrote:
> https://www.t
I wonder if anyone ever completely trusted AMT - maybe some naive excessive
cool-aid drinkers :)
-vb
On Tue, May 2, 2017 at 11:27 AM, ron minnich wrote:
> I wonder if anyone is going to completely trust AMT after this problem. It
> goes back almost 10 years. So for all those users who had it on
Paul,
b: bug references are side effect of google moving to a different bug
tracker internally.
These shortcuts (chrome-os_partner: b:. etc) are parsed and
converted to links by the chrome os gerrit server, like say on this page:
https://chromium-review.googlesource.com/c/451020/, the
Wasn't Martin suggesting to add the results to the poll anonymously,
without revealing the originator's identity?
Come on, guys, Google is a major contributor and benefactor of coreboot,
give it some slack! ;)
--vb
On Fri, Mar 3, 2017 at 2:38 PM, wrote:
> I would also really prefer a non-goo
Incidentally, a few years ago Chirantan and Simon (cced) implemented u-boot
concurrency support for an ARM SOC. I don't remember how much gain it was
bringing, and it did not go into production as it was quite late in the
project cycle.
But they might have some experience to share.
-v
On Tue, F
On Sun, Sep 4, 2016 at 7:42 AM, Nico Huber wrote:
> Hi folks,
>
> I think we kind of agreed that the wiki text about "Commenting" should
> change. So here is my proposal, feel free to edit, add something or just
> ack or complain about it.
>
> > == Commenting ==
> >
> > Comments are good, but the
I actually tend to agree with Julius that it does not make sense to waste 4
lines for a two line comment. So, ideally the tool should be enforcing the
verbose style for comments longer than say 2 lines.
--vb
On Fri, Aug 26, 2016 at 8:48 AM, Martin Roth wrote:
> Can we please just decide on som
I say let's stick with the Linux kernel style, this makes it easier to use
the tools.
And being a much bigger and much more mature codebase, kernel is not a bad
example to follow in general.
--vb
On Wed, Aug 24, 2016 at 12:08 AM, Paul Menzel via coreboot <
coreboot@coreboot.org> wrote:
> Dear c
External declarations in .h files should not be configuration dependent,
maybe this is a simpler fix?
--vb
On Mon, Aug 15, 2016 at 8:55 AM, Trammell Hudson wrote:
> Is it possible to enable CONFIG_TPM with the current head in git?
> On my Lenovo x230, CONFIG_MAINBOARD_HAS_LPC_TPM is selected,
I have not read the entire thread, but just in case it was not
mentioned before: even when the structure elements come together very
snugly on their own, without __packed(), it still is required if the
structure comes over a wire or from a file, etc. as __packed()
guarantees that there is no unali
I am not sure if this happened in coreboot upstream: on some other projects
checkpatch.pl was recently updated to the latest Linux kernel version, and
some more stupid warnings/errors started popping out.
There is a fine controlling checkpatch.pl behavior, .checkpatch.conf in the
coreboot root dir
It's been a while since I looked at it, but why not to pass all
information through the coreboot table? (so that just one pointer
needs to be shared through ACPI).
--vb
On Mon, Apr 18, 2016 at 8:45 AM, Aaron Durbin via coreboot
wrote:
> Hi Folks,
>
> There was a CL going around internal to chrom
Wow, looks like it was an excellent talk, thank you for sharing the slides!
Should we expect an influx of contributions from China now? :)
--vb
On Sat, Apr 9, 2016 at 10:45 AM, Iru Cai wrote:
> Hi community,
>
> I gave a talk about coreboot in my LUG yesterday, and here's my
> slides.
>
> ht
That was quite a fun project :)
I have not read the page in full detail, just curious: was it
necessary to unsolder the chip, was it not possible to program it
using flashrom from Linux command line instead?
Maybe the ME section is write protected - still, writing the rest of
the image could have
On Thu, Feb 4, 2016 at 2:00 PM, Nico Huber wrote:
> On 04.02.2016 22:25, Patrick Georgi via coreboot wrote:
>> 2016-02-04 22:22 GMT+01:00 Martin Roth :
>>> I don't think we need redefinitions of TRUE/FALSE
>> We have no canonical definitions for TRUE/FALSE right now.
>> Contributions that use them
I just looked at the dates - end of January seems a bit odd time to visit,
cold nasty weather, higher likelihood of air travel delays, etc. Not a
major consideration, but something to keep in mind when deciding on
dates...
--vb
On Mon, Nov 2, 2015 at 12:00 PM, David Hendricks
wrote:
> On Sun,
oh, I thought you'd say +1^2 :)
--vb
On Mon, Oct 19, 2015 at 1:05 PM, ron minnich wrote:
> I won't say +1, that's so 2014.
>
> Plus Two!
>
> ron
>
> On Mon, Oct 19, 2015 at 11:53 AM Peter Stuge wrote:
>>
>> Patrick Georgi wrote:
>> > The paragraph in question is:
>> >
>> > You should have
.1 version increase after five years and such dramatic changes in the
product? You should have bumped it by at least 1.0 :)
--vb
On Mon, Jul 13, 2015 at 1:05 PM, Patrick Georgi wrote:
> Dear coreboot community,
>
> It has been more than 5 years since we have “released” coreboot ‘4.0’.
> That la
On Tue, Jun 2, 2015 at 11:38 AM, Steve Goodrich
wrote:
> I got the Chromium version of flashrom to work, but it takes 20 minutes to
> flash/verify the 8 MB device. So, while "working" is far better than "not
> working", it is a bit sluggish. :-)
>
> Any thoughts on speeding it up?
>
usually onl
SPD is some data saved on the memory module, available to the
processor to read to find out memory properies. These data are
protected by a check code (CRC) which allows the CPU to verify that it
read the data correctly. Apparently this check is failing in your
case.
Some likely reasons could be
guys, how do you set up toolchain for building mips targets (or rather
mips target, as there is just one currently :).
I got this flavor from Mentor Graphics site:
mips-linux-gnu-gcc (Sourcery CodeBench Lite 2014.05-27) 4.8.3 20140320
(prerelease)
Copyright (C) 2013 Free Software Foundation, Inc.
That's the spirit!
-vb
On Mon, Mar 23, 2015 at 2:10 AM, Kushagra Kumar wrote:
> I believe impossible can be done I believe I can do it.today m going to do
> smthng to help coreboot wish me luck guys.I will tell type again in 5
> hours.god bless me nd m very excited.
>
>
> --
> coreboot mailing l
Guys, I don't speak for Ron but I don't find his comment (apparently
sent in a emailed to a few folks but then made public (sic!)) elitist,
it was a matter of fact question.
I have been with Chromebook program pretty much from the very
beginning, and I can tell you that the public availability of
On Mon, Mar 2, 2015 at 11:14 AM, Corey Osgood wrote:
> On Mon, Mar 2, 2015 at 12:03 PM, Vadim Bendebury wrote:
>> Not that I care much, but I can't help it: this new symbol looks very
>> much like the infamous SS Bolts:
>> http://www.adl.org/combating-hate/hate-
Not that I care much, but I can't help it: this new symbol looks very
much like the infamous SS Bolts:
http://www.adl.org/combating-hate/hate-on-display/c/ss-bolts.html#.VPSXeFX3-iw
--vb
On Sat, Feb 28, 2015 at 1:59 PM, Stefan Tauner
wrote:
> Hi,
>
> I have put most of my creations online toget
On Thu, Feb 26, 2015 at 8:10 AM, Patrick Georgi via coreboot
wrote:
> 2015-02-26 16:23 GMT+01:00 Emilian Bold :
>> It seems that Coreboot doesn't have reproducible builds yet.
> You're right, it doesn't. One of the major items is probably to
> replace the current build time stamps with something m
On Wed, Feb 18, 2015 at 7:16 AM, Aaron Durbin via coreboot
wrote:
> On Tue, Feb 17, 2015 at 10:44 PM, Alexandru Gagniuc
>
> As I have noted on http://review.coreboot.org/#/c/7924/ it's very
> short sighted to go this route. In assembling a coreboot stack (which
> includes libpayload and the payloa
Ouch, sounds like you really had it with gerrit :)
While I agree that lots of information could be omitted and it would
make more sense if only those who +1'ed or +2'ed a pach were
mentioned, why do you care so mach?
And of course Change-ID is essential: the same patch can have
different SHA1 be
This is what I get when I try it:
"Not Found
The requested URL /praguemeeting/ was not found on this server.
Apache Server at assembler.cz Port 80"
On Sun, Nov 23, 2014 at 11:47 AM, Rudolf Marek wrote:
> Hi all,
>
> Photos from cesnet were already removed but you can find a copy here:
>
> htt
Peter, what browser do you use?!
On Thu, Oct 23, 2014 at 3:18 PM, Peter Stuge wrote:
> ron minnich wrote:
>> is in dublin. How do people feel about dublin?
>
> I was looking into Dublin connections when the Aer Lingus web site
> destroyed the state of my web browser. I for one am not very excited
Note that the version of gerrit used for chromeos allows editing the
commit message through the web interface, no need to re-upload the
patch, and the scores are kept.
Not sure if this is available in the coreboot gerrit though.
--vb
On Wed, Sep 3, 2014 at 12:39 AM, Paul Menzel
wrote:
> Dear c
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