On Tue, Apr 25, 2017, 20:15 Julius Werner wrote:
> I'm very concerned with compatibility. You can't guarantee that coreboot
>> and payload match. And in case of mismatch you get a memory corruption that
>> is very hard to trace. Can we please change signature of cbmem entry?
>
>
> I would rather
I'm very concerned with compatibility. You can't guarantee that coreboot
and payload match. And in case of mismatch you get a memory corruption that
is very hard to trace. Can we please change signature of cbmem entry?
You mentioned having trouble building GRUB. Can you detail those?
What do you m
f06b08a60fe49784c197929b46e22fdb0e1dbbf3 is how to handle. spd.bin is
generated by inteltool
Le Sat, Jan 2, 2016 à 1:49 AM, Vladimir 'phcoder' Serbinenko <
phco...@gmail.com> a écrit :
> I was unable to download as I'm not willing to give dropbox access to my
> contac
I was unable to download as I'm not willing to give dropbox access to my
contacts and I'm too lazy to make a new account now. Anyway the culprit is
unsupported LPC. Here you go: https://review.coreboot.org/12820
Le Sat, Jan 2, 2016 à 1:39 AM, Vladimir 'phcoder' Serbinenko &l
Please send me the full log archive so I can reproduce. Also note: X1
carbon has soldered RAM which will need adjustements
Le Sun, Dec 13, 2015 à 10:59 PM, Gerhard Gappmeier a
écrit :
> Hi all,
>
>
>
> unfortunately autoport didn't work well.
>
>
>
> This is the output on the 1st run:
>
> Unsupp
and copy all these commits to this separate branch, which means
it would be abandoned.
>
>
>>> On 11/07/2015 10:18 AM, Alex Gagniuc wrote:
>
>>
>> such malevolent plans are a great insult to a bright spirit of coreboot !
>>
>
> I'm insulted by your port
s code will be
allowed to stay in its AGESA shape until a stable "Native Init" replacement
will be introduced
Best regards,
Vladimir Shipovalov
On 6 November 2015 at 20:34, Timothy Pearson <
tpear...@raptorengineeringinc.com> wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Has
negatively affect a support for
alive boards, because such malevolent plans are a great insult to the
bright spirit of coreboot project !
Best regards,
Vladimir Shipovalov
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Le 3 nov. 2015 6:46 PM, "Aaron Durbin" a écrit :
>
> On Tue, Nov 3, 2015 at 10:28 AM, Vladimir 'phcoder' Serbinenko
> wrote:
> > The code itself looks good but I'd like more details. Reading 0x
> > shouldn't cause reboot. Why does it?
The code itself looks good but I'd like more details. Reading 0x
shouldn't cause reboot. Why does it?
Le 1 nov. 2015 3:53 PM, "Andrei Borzenkov" a écrit :
> I was debugging problem reported by user on Dell Dimension 8300 - it
> rebooted when doing "ls -l". It turned out, the problem was t
to skip AGESA build without moving it to a branch and separating from the
rest of the coreboot code . So this is seen as a really bad excuse
Best regards,
Vladimir Shipovalov
On 3 November 2015 at 01:14, Peter Stuge wrote:
> Alex G. wrote:
> > >> users of AGESA can continue to
anch! That approach will allow
coreboot developers with AMD boards to avoid spending time on backporting
the changes and concentrate on developing and testing the latest coreboot
builds from a master branch
Best regards,
Vladimir Shipovalov
On 28 October 2015 at 11:32, Patrick Georgi wrote:
>
le" servers
are affected)
Hopefully this blobgesa will be open sourced eventually - its not that far
from reality because AMD open sourced a lot of stuff during the past
months... Also it will be very interesting to see how AMD Zen platforms
will behave
Best regards,
Vladimir Shipovalov
On 28 O
SIGNED MESSAGE-
> Hash: SHA1
>
> On 10/27/2015 03:10 PM, Vladimir wrote:
> > It would be really wrong to remove the whole AGESA code: there are
> > AMD-based products which are still very alive and actively sold (at the
> > developing markets) Moving the support for t
It would be really wrong to remove the whole AGESA code: there are
AMD-based products which are still very alive and actively sold (at the
developing markets) Moving the support for these products to a separate
coreboot branch, could create many inconveniences for those AMD product
owners who would
Is size L ok for you?
Le Wed, Oct 7, 2015 à 8:20 AM, Marc Jones a écrit :
> Hi Vladimir,
>
> I'd love a shirt. See you in a few days.
>
> Marc
>
> On Tue, Oct 6, 2015, 11:53 PM Vladimir 'phcoder' Serbinenko <
> phco...@gmail.com> wrote:
>
>>
Currently remaining are:
8 x L T-shirts
1 x XL T-shirts
1 x yellow cup
3 x plates
3 x baseball cap
8 x magnets
5 x coasters
Every item under 20€
Images:
http://coreboot.org/Coreboot_conference_Bonn_2015
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>
>
> I would like to order 3 plates, 1 white, 1 black, 1 pink cup and 1 magnet.
>
All reserved for you.
> If you have extra white cups I'll buy those too.
>
> Sorry, only 1 was left before this e-mail.
> If I don't make it in person I'll ask if someone might courier cash
> and goodies on my beha
Le Tue, Oct 6, 2015 à 10:55 PM, Peter Stuge a écrit :
> Vladimir 'phcoder' Serbinenko wrote:
> > Reminder, please write me if you want any of this. Right now only
> > Ron Minnich and echelon have ordered. I've added pictures at
> > http://coreboot.org/C
Reminder, please write me if you want any of this. Right now only Ron
Minnich and echelon have ordered. I've added pictures at
http://coreboot.org/Coreboot_conference_Bonn_2015
Le Wed, Sep 9, 2015 à 9:29 AM, Vladimir 'φ-coder/phcoder' Serbinenko <
phco...@gmail.com> a écri
Hello, all. My girlfriend Maria (CC'ed) would like to organize some
goodies for coreboot meeting. Already available are black T-shirts:
2 x M, 8 x L, 1 x XL according to my notes, it's no guarantee, I can't
double-check now as I'm travelling.
Expected price is under €20 for any of items.
Capacity i
Thank you very much for solving this riddle!
And one more question for Rudolf: please tell, are you using atomDis
utility to disassemble atombios into C code? Or there are some other
special tools, which probably have more recent versions? (latest version of
atomDis is already 4 years old...)
On 3
ot necessarily limited to my hardware ( Lenovo G505s ) , and
maybe could lead to some other problems
Please tell your opinion, is it a bug or I am wrong at something?
Best regards,
Vladimir Shipovalov
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On 31.05.2015 19:27, Matthias Apitz wrote:
> El día Sunday, May 31, 2015 a las 06:45:48PM +0200, Vladimir
> 'φ-coder/phcoder' Serbinenko escribió:
>
>> Good news: now it's possible to have them in black as well.
>> I received up to now only one request to whi
interested), quantity and if you want it single or
double-sided printing.
Please tell me until Friday.
@Carl-Daniel: Still waiting for that PDF.
On 21.05.2015 15:41, Vladimir 'phcoder' Serbinenko wrote:
> Apparently original mail didn't make it to the list. Resent
>
&g
On 21.05.2015 16:19, Michael Gerlach wrote:
> Okay here we go...
>
> I memtested the modules again and as expected no defect was found. So i
> retried latest master today and quite unusually it just boots up.
>
Quite possibly you were just missing microcode update.
> It does not reach payload-sta
Le Sat, May 23, 2015 à 4:46 AM, Michael Gerlach a
écrit :
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Hi Patrick!
>
> Uhm - I do not explicitly compressed it. I just added it to config..
>
> Extracted it via
>
> echo 1 > /sys/devices/pci\:00/\:00\:02.0/rom
> cp /sys/devices/pci0
Le 21 mai 2015 13:01, "Carl-Daniel Hailfinger" <
c-d.hailfinger.devel.2...@gmx.net> a écrit :
>
> On 21.05.2015 12:51, Vladimir 'phcoder' Serbinenko wrote:
> > A contact of mine proposes to print coreboot T-shirts for the community.
> > Black printin
A contact of mine proposes to print coreboot T-shirts for the community.
Black printing on white T-shirt. Expected price is 30€-35€ + shipping from
CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed
in Russia. I need to know who wants one and sizes by June 5th. For payment
Apparently original mail didn't make it to the list. Resent
-- Forwarded message --
From: Vladimir 'phcoder' Serbinenko
Date: Thu, May 21, 2015 at 2:29 PM
Subject: Re: [coreboot] Coreboot T-shirts
To: Carl-Daniel Hailfinger
Cc: coreboot
Le 21 mai 2015 13:0
lso, on my motherboard there was no MXIC chip, but cFeon QH32-104HIP bios
chip instead. As you see, lots of things could be added to Coreboot G505s
wiki. I've asked a coreboot wiki account so that I could improve g505s
page: add new information, and clarify older as well
On 17 April 2015 at 11:45,
t x86/x86_64 branch.
P.S. In addition to Lenovo G505s, I was very happy to find out that -
thanks to latest contributors - coreboot is now supporting the ASROCK
IMB-A180 and Biostar AM1ML which are based on AMD AM1 platform
(architecture family 16h, Puma/Jaguar SoCs are compatible) Maybe some of
t
; list
( http://www.coreboot.org/User_talk:MrNuke/LTS_Candidates ) have A10-5750M
as well and seem to be more "reasonably available" than G505S, at least for
your country. But, despite having a somewhat similar hardware, nobody
ported a coreboot to them yet :P
Best regards,
Vladimir Shipova
Could you provide links within the EU with (online) shops still selling
> the A10 variant and having some actual stock?
>
> --emi
>
> On Mon, Apr 6, 2015 at 6:45 PM, Vladimir wrote:
>
>> Yes, in addition to A10-5750M based G505S there are also A8 and A6 ones.
>> But th
shiba
> Satellite C50D-A mentioned in the wiki.
>
> --emi
>
>
> On Mon, Apr 6, 2015 at 1:45 PM, Vladimir wrote:
>
>> Dear coreboot developers,
>>
>> Francis Rowe (main Libreboot developer) has hinted an idea about adding
>> Lenovo G505S to Coreboot LTS
AMD HD 8570M (dual graphics)
*3)* 8650G + AMD R5 M230 ( dual graphics, slightly more powerful than "2)" )
Are these modifications all supported by Coreboot? And would be there any
additional difficulties regarding modifications with dual graphics?
Your answers and opinions will be very welc
1 wrote:
> No. I not solved this problem.
>
> 2015-04-03 17:08 GMT+04:00 Vladimir :
>
>> > On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote:
>> >> I'm trying to run Coreboot on Lenovo G505s and have a problem:
>> >> - backlight of LCD is not turn on
1 wrote:
> No. I not solved this problem.
>
> 2015-04-03 17:08 GMT+04:00 Vladimir :
>
>> > On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote:
>> >> I'm trying to run Coreboot on Lenovo G505s and have a problem:
>> >> - backlight of LCD is not turn on
> On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote:
>> I'm trying to run Coreboot on Lenovo G505s and have a problem:
>> - backlight of LCD is not turn on. But on the external LCD (by CRT
>> connector) is all good.
>>
>> Could you help me with a solution to this problem?
Sorry for such a long reply
On 08.12.2014 01:00, Charles Devereaux wrote:
> Sorry, but if it is like the X60 it can not be made the work.
>
> Just like in the WWAN slot, but in reverse, the USB lines are not wired
> on the WLAN slot.
>
> IIRC this is not the case on the X201 (a very nice machine, but coreboot
> support may
> > To emulate rfkill functionality, just write directly to the ec, for ex
> > to turn on wwan and wifi:
> > ./ec_access -w 0x3a -v 0x60
> >
> Usecase?
>
>
> Example: I have a wwan card, but I mostly use it for GPS. I can save
> some power by turning it off without rebooting,
On 03.12.2014 23:32, Charles Devereaux wrote:
> Hello
>
> As explained before, thinkpad-acpi can't control the non-wifi radio like
> bluetooth or wwan, because it expects some ACPI entries that aren't
> there - so there is no rfkill control for these, even if some
> non-working entries are shown w
Hello, all. I know I've signed up to fix board-status and cmos but I
don't want to go through painful reviews, so I'm not going to do this,
even though maintaining current CMOS stuff is a pain in itself.
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On 22.11.2014 17:28, John Lewis wrote:
>
>
> On 22/11/14 15:55, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> On 22.11.2014 12:22, John Lewis wrote:
>>>
>>>
>>> On 21/11/14 21:58, Vladimir 'φ-coder/phcoder' Serbinenko wrot
On 22.11.2014 12:22, John Lewis wrote:
>
>
> On 21/11/14 21:58, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> On 14.11.2014 12:44, John Lewis wrote:
>>> Hey y'all,
>>>
>>> I've modified the board-status script to have as few ext
On 14.11.2014 12:44, John Lewis wrote:
> Hey y'all,
>
> I've modified the board-status script to have as few external
> dependencies as possible, be a self-extracting, self-running "binary".
> and removed the time-stamp to keep the number initial commits down. Feel
> free to tell me how bad it is
;
>
> On Sun, Oct 12, 2014 at 4:39 PM, Vladimir 'φ-coder/phcoder' Serbinenko
> mailto:phco...@gmail.com>> wrote:
>
> On 12.10.2014 13:03, Vipin Gahlaut wrote:
> > Ok, I changed CONFIG_BOARD_ROMSIZE_KB_ to 512 directly in .config as
> > thi
_KB_16384 is not set
> CONFIG_COREBOOT_ROMSIZE_KB=512
> CONFIG_ROM_SIZE=0x8
>
>
> On Sun, Oct 12, 2014 at 4:21 PM, Vladimir 'φ-coder/phcoder' Serbinenko
> mailto:phco...@gmail.com>> wrote:
>
> On 12.10.2014 12:44, Vipin Gahlaut wrote:
> >
On 12.10.2014 12:44, Vipin Gahlaut wrote:
> I tried changing under main mainboard -> rom chip size but does not seem
> to be helping. If I look at .config I suspect that the reason is
> CONFIG_BOARD_ROMSIZE_KB_256=y which doesn't change even if I change ROM
> size in main board.
CONFIG_BOARD_ROMSIZ
On 12.10.2014 11:57, John Lewis wrote:
> Hi,
>
> It's in "Chipset Options" -> "Size of CBFS filesystem in ROM" - 0x20
> or 0x40 will work.
>
This is only for recent intel chipsets.
> Cheers,
>
> John.
>
> On 12/10/14 10:51,
Hello, all. I've updated
http://www.coreboot.org/PragueMeetingHardware#phcoder . If somebody
wants me to bring sth, please add a paragraph there, otherwise, I won't
take almost anything.
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On 12.10.2014 08:03, Vipin Gahlaut wrote:
> Hi,
>
> I have cloned latest coreboot and trying to build with grub2 as payload.
> in make menuconfig I select grub2 instead of seabios. when I fire make
> command it checkout latest grub and that fails to build. for 2 reasons.
>
> 1. Due to some initia
On 11.10.2014 03:20, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
> On 11.10.2014 03:03, ron minnich wrote:
>> Android defaults sometimes surprise me.
>>
>> When we've had this kind of issue in the past a disassembly diff of
>> good vs bad has sometimes
On 11.10.2014 03:03, ron minnich wrote:
> Android defaults sometimes surprise me.
>
> When we've had this kind of issue in the past a disassembly diff of
> good vs bad has sometimes led to diagnosis. I think you have a rough
> idea what's broken so start there. Painful but necessary.
>
.car.dat
Success. Addresses are slightly different and new XSDT table but both
are ok and expected.
On 11.10.2014 00:16, Paul Menzel wrote:
> Dear Vladimir,
>
>
> Am Mittwoch, den 08.10.2014, 21:29 +0200 schrieb Vladimir Serbinenko:
>> Vladimir Serbinenko (phco...@gmail.com) just upload
On 21.09.2014 04:12, ron minnich wrote:
> Here's the problem. There is caching of the DRAM configuration going
> on. So, a restart is not stateless.
>
> I would be happier if you could guarantee that the mrc cache is
> disabled, or never used, each time you change the dram setup (move
> DIMMs, wha
On 09.09.2014 20:52, Luigi Bai wrote:
> Per the wiki, I am offering this information to try to determine the
> status of coreboot support, especially for Intel/PM965 or Intel/82801H.
> I didn't see either under the lists of supported hardware
Unsupported, chipset unsupported. There is a very experi
On 06.09.2014 00:31, H. Peter Anvin wrote:
> On 09/05/2014 02:23 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> On 06.09.2014 00:18, ron minnich wrote:
>>> Vladimir can you point me to that patch? This sounds
>>> interesting.
>>>
>> https:/
On 06.09.2014 00:19, ron minnich wrote:
> I don't think it's random at all. Vladimir can confirm, but if he is
> caching the RAM parameters, then this 'solution' will work for you
> until the next time you reflash coreboot, or change your dram type, at
>
On 06.09.2014 00:18, ron minnich wrote:
> Vladimir can you point me to that patch? This sounds interesting.
>
https://lkml.org/lkml/2010/8/25/190
> ron
>
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> I'm not a fan of Coreboot having invented its own nonstandard hacks, but
> I guess it is pretty much unavoidable.
It's completely avoidable. The stub can copy this information to
standard framebuffer info structure. The only missing thing is to apply
patch by cjwatson or mjg59 (I'm not sure now
This code assumes that payload didn't change video mode which is
improper assumption if you're not a payload.
On 04.09.2014 12:25, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> arch/x86/Kconfig | 12 +++
> arch/x86/kernel/Makefile | 1 +
> arch/x86/kernel/coreboot.c |
On 01.09.2014 22:19, Charles Devereaux wrote:
> Hello
>
> I'm interested in WWAN support, mostly for the GPS features and the cool
> things you can do with them (like a stratum ntp server).
>
Most GPS receivers don't have enough precision for any timing.
> I was told a EM770W doesn't even need a
morrow night or wednesday.
>
> I will also report you the ACPI EC results.
>
> Did you only had to activate CONFIG_ACPI_DEBUG to get these logs?
>
> Thanks
> Charles
>
>
>
> On Mon, Aug 25, 2014 at 5:02 PM, Vladimir 'φ-coder/phcoder
On 26.08.2014 17:53, Charles Devereaux wrote:
> My understanding is that the OS does the call that correctly, but that
> coreboot ASL tables only expect one argument.
Please provide a refrence when doing such bold claims. LED method is not
specified in ACPI, so assuming that it takes any particular
On 26.08.2014 08:50, Paul Menzel wrote:
> Dear Charles, dear David,
>
>
> Am Montag, den 25.08.2014, 11:21 -0600 schrieb David Hubbard:
>
>> I'm focusing in on this error message first:
>>
>> ACPI Warning: For \_SB_.PCI0.LPCB.EC__.LED_: Excess arguments - needs 1,
>> found 2
>>
>> Can you take a
On 25.08.2014 23:28, ron minnich wrote:
> A friend asks me how to disable the usb stack in his bios. I have no
> clue, anyone?
>
Doesn't sound like end goal. But I'd go through setup menu to see if
something fits his *end* goal (disabling usb stack sounds like means to
goal, not the goal itself).
On 25.08.2014 22:53, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>>> Ideally, the DSDT should be fixed within coreboot, but this goes beyond
>>> my present abilities.
>> Not true. Just do the same changes to the corresponding *.asl files in
>> coreboot
>> Ideally, the DSDT should be fixed within coreboot, but this goes beyond
>> my present abilities.
> Not true. Just do the same changes to the corresponding *.asl files in
> coreboot repo and send the patch to gerrit. Other than a layer of
> preprocessing, it's exactly the same code as you got fro
On 25.08.2014 04:39, Charles Devereaux wrote:
> Hello
>
> Previously
> (http://www.coreboot.org/pipermail/coreboot/2014-July/078320.html) I
> mentioned that 3 bugs seemed to be related to the DSDT:
> - missing ACPI events when the stylus is inserted/removed
How is the OS supposed to react to them
On 10.08.2014 21:06, John de la Garza wrote:
> I understand that the calling functions in 32 bit C uses the stack and
> this is why coreboot needs to use cache as RAM. Doesn't 64 bit C use
> registers to pass arguments to functions? If this is the case why not
> run in 64 bit mode?
>
> Also, eve
On 06.08.2014 00:08, Peter Stuge wrote:
> Simon Andrä wrote:
>> I want use coreboot but i dont know if my system is supportet:
>> I have an Acer Predator G3620
>
> It isn't.
>
>
>> I hope someone can help me
>
> As always with open source you have to help yourself.
>
Or hire someone to do it.
On 19.07.2014 07:42, Charles Devereaux wrote:
> Hello,
>
> On Wed, Jul 9, 2014 at 2:15 AM, Denis 'GNUtoo' Carikli
> mailto:gnu...@no-log.org>> wrote:
>
> My pomona clip had issues with its contact pins(the ones in contact
> with the flash chip) over time, so I unmounted it and repaired it
On 20.06.2014 20:43, Patrick Georgi wrote:
> Am 20.06.2014 22:40, schrieb Vladimir 'φ-coder/phcoder' Serbinenko:
>> (think MAC address).
> I guess PC technology is finally beyond requiring those at fixed magic
> offsets. Some of our chipsets still need it that way.
&
On 20.06.2014 20:08, Patrick Georgi wrote:
> Am 20.06.2014 22:01, schrieb Rafael Vanoni:
>> Take serial number, for example. I'd like each different system that I
>> build to have its own serial number, and building coreboot for every
>> serial number doesn't scale.
> We have an .id section just be
On 11.06.2014 09:46, derpeter wrote:
>
> I tried this last month. I cherrypickt everything execpt the video fix
> and got a working coreboot.
> Sadly i could not bring the wacom to work but i'm not sure if its a
> problem of coreboot or linux.
Submit logs then: Xorg log, dmesg and coreboot log.
On 05.04.2014 19:02, mrnuke wrote:
> When an event happens, on the other hand, like a hotkey, or AC is removed, it
> does not generate an SCI that would lead to a query call (_Qxx). Instead it
> spits out an SMI. I know for a fact that the SCI and SMI GPEs are where we
> expect them to be.
What
On 29.03.2014 08:41, Patrick Georgi wrote:
> Am Samstag, den 29.03.2014, 08:30 +0100 schrieb Vladimir
> 'φ-coder/phcoder' Serbinenko:
>> Do I get it correctly that your main problem is the heavy use of
>> #include romcc requires? If so why don't we just create a
On 29.03.2014 07:45, Stefan Reinauer wrote:
> * Andrew Wu [140327 14:00]:
>> Sorry, I checked Vortex86EX CPU datasheet, but it seems there is no
>> workaround can do it.
>>
>> So if I want to get rid of romcc, maybe I have to write DRAM init code
>> in assembly, That is not very easy. :(
>
> Don
On 26.03.2014 00:33, The Gluglug wrote:
> --> alternatively:
> ship coreboot without anything in src/mainboard.
> have git repositories for each vendor/mainboard.
> user downloads what they need, and a default .config for the board of
> their choosing.
>
Git is developpement tree, not user-fetch t
On 25.03.2014 06:34, ron minnich wrote:
>
>
>
> On Mon, Mar 24, 2014 at 10:20 PM, Vladimir 'φ-coder/phcoder' Serbinenko
> mailto:phco...@gmail.com>> wrote:
>
>
> I don't see how this prevents any of my propositions for the bulk of the
>
On 25.03.2014 02:33, Stefan Reinauer wrote:
> * David Hubbard [140323 20:33]:
>> On Sun, Mar 23, 2014 at 12:58 PM, Vladimir ' -coder/phcoder' Serbinenko <
>> phco...@gmail.com> wrote:
>>
>> On 23.03.2014 19:24, ron minnich wrote:
>>
On 23.03.2014 19:24, ron minnich wrote:
> I have friends who commit to grub2, and there seem to be gatekeepers
> there; how do you manage that process?
In case of grub2 I admit we have exactly the problems I described. I'm
open to having more maintainers but right now it doesn't seem to be
feasible
On 23.03.2014 19:24, ron minnich wrote:
> So I believe the problem is not the idea of gatekeepers, but the
> manner in which they are proposed to work. Can you tell me what about
> this upsets you? I want to understand.
The problem is that the proposal is that all commits go through
gatekeepers. It
On 23.03.2014 04:10, Peter Stuge wrote:
> That isn't too different from creating a fork?
Fork is better. With fork we don't have to deal with the same people who
pushed the community out in the first place.
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On 20.03.2014 22:33, Stefan Reinauer wrote:
> During this time we collected over 250 different
> mainboards. A great achievement,
I suppose that most of boards were contributed by non-commercial
community. Yet now you propose to basically kill this chicken nesting
golden eggs and make coreboot comm
On 21.03.2014 01:39, Carl-Daniel Hailfinger wrote:
> Hi Stefan,
>
> streamlining development and maintenance is definitely absoutely
> worthwhile. Getting rid of unmaintained code is also a good thing. The
> guidelines presented in your mail look mostly good IMHO, but I'd like to
> comment on a fe
On 20.03.2014 22:33, Stefan Reinauer wrote:
> coreboot for the 21st century
>
> setting up the project for the next decade
>
> Purpose: Purge all boards / chipsets / cpus that require ROMCC in
> romstage and known broken chipsets (sc520, i855)
>
> coreboot is now officially 15 years old. One and
On 20.03.2014 13:45, Peter Stuge wrote:
> Vladimir 'φ-coder/phcoder' Serbinenko wrote:
>> On 20.03.2014 11:25, Allen Yan wrote:
>>> Hi, David,
>>>When at AsusTek Suzhou, my work is mainly responsible for bios
>>> porting and fixing bug.
>&
On 20.03.2014 13:34, Shant Kehyeian wrote:
> No I just gave in menuconfig the snow board ...and then as a payload I
> chose the GRUB2...that's what I meant ...:)
>
Keep list CC'ed.
I'm surprised it compiled at all. It should have error'ed out.
>
> On Thu, Ma
ompile GRUB2 for ARM coreboot but it's
unlikely to work. I'm under impression that you compile for wrong
mainboard altogether (you've chosen mobo in make menuconfig, right?)
>
> On Thu, Mar 20, 2014 at 12:23 PM, Vladimir 'φ-coder/phcoder' Serbinenko
> mailto:p
fragmentation of ARM it may even mean that only
Linux-based works on your machine.
>
> On Thu, Mar 20, 2014 at 4:05 PM, Vladimir 'φ-coder/phcoder' Serbinenko
> mailto:phco...@gmail.com>> wrote:
>
> On 20.03.2014 12:12, Shant Kehyeian wrote:
> > Hello,
&
On 20.03.2014 12:12, Shant Kehyeian wrote:
> Hello,
> I have Samsung ARM chromebook series 3 "Snow" and I am trying to flesh
> it and change the boot process.
> So I build a coreboot.rom for that, but before I start to do that I
> would like to ask about the payload. When I did the "make menuconfig
IOS
code? If so which papers did you sign and under what license did you get
them? Depending on the answers it may partially or fully disqualify you
from contributing to coreboot.
> Interesting experience, but memories will fade! Details can't be
> remembered clearly.
>
>>
On 19.03.2014 21:06, Allen Yan wrote:
> As Stefan Tauner's suggestion, maybe porting coreboot to new mainboard
Just a quick note: for porting to new chipset to be accepted, you need to:
1) Justify why this chipset is relevant. E.g. old chipsets most probably
aren't.
2) Prove that you're able to do
On 17.03.2014 20:39, Grim Schjetne wrote:
> Bernie Innocenti writes:
>
>> First of all, thank you very much for porting Coreboot to the X230.
>
> Indeed, this has made me all the more interested in the Coreboot
> project. With an X201 and an X230 port, perhaps there is some hope
> for an X220 po
On 17.03.2014 17:08, Bernie Innocenti wrote:
> Hello Vlad!
>
> First of all, thank you very much for porting Coreboot to the X230.
>
> I'm following your instructions [1] to build a coreboot image from head,
> but I'm not sure how to configure things in menuconfig. Would you mind
> sharing your .
On 17.03.2014 08:00, Mono wrote:
> Who knows, it might(!) fix some 5 year old bug?
Then it should be no problem for you to point one to us.
coreboot is not openhardware. It never was and never will be.
Openhardware is the only way to know what your hardware actually.
Coreboot is only how to kick th
@ron: please provide more information about your qemu: version, how
built, options, patches,... Try -M pc-q35-1.7 and -M pc-i440fx-1.7. Try
specifying --no-kvm and --enable-kvm. Speyifying -cpu may help as well.
From my experience with GRUB, qemu has following flaws:
- From version to version they
On 02.03.2014 09:01, Muhammad Ramshad wrote:
> When i search through the projects and organizations the coreboot
> project grabbed my focus towards it because i am more interested in
> Digital System Design and hardware a level development like processor
> design and ISA designs.
And absolutely no
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