Hi All,
This is my first email to coreboot open source team
Does coreboot 4.8/4.9 support
*Specific absorption rate* (*SAR*)
How does Linux or Kernel driver uses the SAR Tx Power limits, Anyone
working on this task, Kindly respond
regards
Galla
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coreboot mailing list: coreboot@coreboot.org
h
Hi ,
How does the coreboot picks the cpu microcodes
as a blob or ASCII ?
Tried both option GENERATE FROM TREE and INCLUDE EXTERNAL HEADER
In Memory it appears it picks the ASCII file, but not a blob
intel/cpu/baytrail/microcode/M0130679901.h
0x0001, /* Header Version */
0x0901, /* Pat
This issue is sorted out
cpu_microcode_blob.bin matches the ".h" file for microcode
the SoC still fails at this point
msr.lo = (unsigned long)m + sizeof(struct microcode);
msr.hi = 0;
*wrmsr(0x79, msr);*
Any clues?
On Fri, Sep 28, 2018 at 5:28 PM galla rao wrote:
> Hi ,
> 0x,
>
> And try again...
> Jose Trujillo.
>
> ‐‐‐ Original Message ‐‐‐
> On Friday, September 28, 2018 7:28 PM, galla rao
> wrote:
>
> Hi ,
>
> How does the coreboot picks the cpu microcodes
>
> as a blob or ASCII ?
>
> Tried both
Hi All,
Am facing Gfx Enablement failure, i don't see any Video output on my screen
Config file has below settings
CONFIG_VGA_BIOS_ID="8086,0f31"
CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_VGA_BIOS=y
CONFIG_UDELAY_IO is not set
CONFIG_DCACHE_RAM_BASE=0xfef000
uld choose vesa framebuffer
> option and text mode in seabios
> JT
>
>
> ‐‐‐ Original Message ‐‐‐
> On Thursday, November 8, 2018 1:08 PM, galla rao
> wrote:
>
> Hi All,
>
> Am facing Gfx Enablement failure, i don't see any Video output on my screen
>
Hi All,
am trying to save NVRAM variables which are modifed in Uefi Payload, but i
could not save it.
what is the role of uefi_nvs.bin file?
coreboot/intel/mainboard/intel/bayleybay_fsp/uefi_nvs.bin
Even the boot order does not save into NVRAM variables
Can some one help me on this, Base a
will try to do it
> myself.
>
> Jose.
>
>
>
> ‐‐‐ Original Message ‐‐‐
> On Wednesday, November 21, 2018 7:28 PM, galla rao
> wrote:
>
> Hi All,
>
> am trying to save NVRAM variables which are modifed in Uefi Payload, but i
> could not save it.
>
Hi All,
Does Tianocore payload supports Variable services for storing variables in
SPI Flash
The default has
*In CorebootPayloadPkgIa32X64.dsc *
* MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf*
Ideally it should have below drivers for Variable services to work
C
Video Mode in Coreboot
*CorebootLog*
coreboot video frame buffer information
physical_address: 0xC000
*x_resolution: 0x400*
*y_resolution: 0x300*
bits_per_pixel: 0x20
bytes_per_line: 0x1000
red_mask_size: 0x8
red_mask_pos: 0x10
GOP UEFI driver (Tiano payload) is expected to report 4 modes
GOP
Hi All,
Good Morning!
would like to know from coreboot community a query on Secureboot keys!
Is there a standard way to add SECUREBOOT keys into coreboot build process?
Typically to sign & authenticate any UEFI application or OS loader, Keys
need to be enrolled into BIOS.
Shed some knowledge,
Hi All,
To pull cross compile tools in Coreboot the below command is run,
make crossgcc-i386 CPUS=6
Is there a step or a command to clean all the tools that got installed ?
Regards
Ranga
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Thank you Nico for response, it clears xgcc folders in crossgcc
How about tarballs that were also downloaded ?
On Tue, Feb 12, 2019 at 6:39 PM Nico Huber wrote:
> Hi Ranga,
>
> On 12.02.19 15:24, galla rao wrote:
> > To pull cross compile tools in Coreboot the below command i
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