[coreboot] Patch set updated: 5cb524a AMD F14 southbridge update

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/135 -gerrit commit 5cb524a357dc0c3b4f959ca44a50b00c1dd76b77 Author: Kerry She shekairui at gmail.com Date: Thu Aug 18

[coreboot] New patch to review: 5c1e354 AMD SB800 southbridge update

such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen perh52 at runbox.com Signed-off

[coreboot] New patch to review: 000ea38 AMD F14 Rev C0 update

commit 000ea3878c8d28dc79897c997f5ca82366542da8 Author: Kerry She shekairui at gmail.com Date: Thu Aug 18 18:58:40 2011 +0800 AMD F14 Rev C0 update Add AMD Family14 Rev C0 cpu id The second line is in my opinion even a better commit summary. How about family14: Add AMD

[coreboot] E350M1 does not POST

Hi, Upon booting, I get this: [...] you could try commit 0df0e14fb, that may or may not work, the commit after that broke fusion boards completely, apparently. Florian Thank you! I can confirm that 0df0e14fb works properly. -Marshall Frank, It looks like we have a regression. Is

[coreboot] [PATCH] ASRock E350M1: enable superio hardware monitor access

This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level

[coreboot] Patch set updated: ea7a21e AMD F14 southbridge update

The proposed get_sb800_revision is incomplete. We know that at least SB810, SB820M and SB850 exist, and that production ASIC revisions are A12, A13 (and perhaps later). Since Frank is at AMD I guess he can obtain the full set easily. The SB8xx device in the Asrock E350M1 has rev_id = 0x42 and

[coreboot] Patch set updated: ea7a21e AMD F14 southbridge update

Looking at src/southbridge/amd/cimx/sb800/late.c static void usb_init(struct device *dev) { + printk(BIOS_DEBUG, SB800 - Late.c - usb_init - Start.\n); usbInitAfterPciInit(sb_config); commonInitLateBoot(sb_config); + printk(BIOS_DEBUG, SB800 - Late.c - usb_init -

[coreboot] ASRock e350m1: network problems

On the SATA MSI disable problem: calling sbAfterPciInit from cpu_bus_init succeeds in disabling MSI for SATA. So now the linux driver correctly does not try to enable MSI for SATA. But that code is not minimal and might not be the right thing to do. Back to the ethernet problem. Comparing PCI

[coreboot] ASRock e350m1: network problems

Start by comparing interrupt setup and interrupt rates with factory BIOS. Then drill all the way down through the five-six groups of registers that are relevant for interrupt handling in the hardware and compare differences selectively based on ideas gathered from initial behavior

[coreboot] ASRock e350m1: network problems

On the ASRock E350M1 I see slow data rates (=10% of full rate) for incoming data transfers using the onboard gigabit NIC. There are kernel log messages like r8169 :03:00.0: eth0: link up NOHZ: local_softirq_pending 08 repeated 10 times, followed by messages like net_ratelimit: 75 callbacks