Hi Patrick.
> I'm not sure about Siemens' hwilib: if that's imported, it remains there, if
> this version is written for coreboot, src/drivers/siemens perhaps?
This code is basically a pure software library to access defined fields within
a binary image kept inside CBFS.
Since there is no hardw
Hi Anatolii.
The debug version of FSP is a separate build of the FSP binary which is hard to
get other than from Intel.
In addition, the debug versions of the FSP I ever had my hands on were not able
to pass DRAM init in FSP-M.
If you, contrary, simply enable UART log in the non-debug FSP binar
We could introduce a Kconfig switch per driver and let the driver handle the
bit.
Everything else could be removed. This would make it easier to track the usages.
It would be nice if we could agree on a naming scheme so that all switches are
named similar which would make it easier to track the u
Dear coreboot community.
A few of you may already have noticed that one of this years GSoC projects
coreboot hosts is the adding of "Address Sanitizer" feature to our code base.
This project has been taken by Harshit Sharma and he has spent the first period
of coding on adding the needed code an
Hi Harshit and welcome in the coreboot community.
I which you a good start with your project and hope you will feel well inside
our community.
If there are questions from your side do not hesitate to drop an e-mail on this
list or get in touch with people on IRC.
Werner
Von: Harshit Sharma
Ge
Hi.
If you decide to use MemoryDown, you need to provide the SPD data to FSP in a
buffer.
If you use normal DIMM configuration, FSP is able to read SPD data form the SPD
EEPROM on its own.
So yes, I can confirm that FSP handles SPD EEPROM on its own.
Werner
Von: Naveen Chaudhary
Gesendet: Do
Hi Naveen.
I am not sure that FSP supports mixed setup with both memory down and DIMMs at
the same time. At least there is just one UPD parameter telling that you either
have DIMM or memory down enabled (MemDownEnable).
So I haven't figured out how to tell FSP which channel is memory down and wh
Hi Christian.
In APL there are special tuning registers for the SATA lanes which may need an
adjust.
The fact that stock UEFI runs without issues may be explained that UEFI touches
this registers.
Do you have access to related intel docs? Otherwise have a look at
https://review.coreboot.org/pl
If I am not mistaken at least 00:03.2 and 00:03.3 are the integrated PCIe-Ports
of the IOU (PEG-port) and their availability depends on the PCIe bifurcation of
the associated PEG-port.
You can configure the bifurcation over the FSP-parameters
"ConfigIOU2_PciPort1" and "ConfigIOU1_PciPort3". If
e: Question how to write protect flash
Yes its sandy bridge. What is proper way to do this though. On flash descriptor
(and if so, how?) or through coreboot option?
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‐‐‐ Original Message ‐‐‐
On Monday, July 15, 2019 12:37 AM, werner@siemens.com
wrote:
IIRC X220 uses Sandy Bridge. I think there is a flag somewhere in the
descriptor where you can lock down your BIOS-region as read-only for the x86
host.
I never have tried it but in theory this should lead to errors on every write
attempt to the BIOS region therefore disabling write access to th
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