Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

On Fri, Apr 23, 2010 at 10:59:51PM +0200, Rudolf Marek wrote: Thanks, it is in as Committed revision 5485. While we are at the tinybootblock. Kevin do you plan to convert the epia-cn too? What about to implement there the PSON gating so SMB hack is not needed anymore? I didn't need to do

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

On 4/22/10 11:41 PM, Rudolf Marek wrote: Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work. We cannot walk anything else than PCI bus 0 because HT is not setup yet. Signed-off-by: Rudolf Marek

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Thanks, it is in as Committed revision 5485. While we are at the tinybootblock. Kevin do you plan to convert the epia-cn too? What about to implement there the PSON gating so SMB hack is not needed anymore? Thanks, Rudolf -BEGIN PGP

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Following code does work: static void bootblock_southbridge_init(void) { /* ROM decode last 8MB FF80 - on VT8237S/VT8237A */ /* ROM decode last 4MB FFC0 - on VT8237R */ device_t dev; /* Power management controller */

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi again, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); pci_write_config8(PCI_DEV(0,0x11,0), 0x41, 0x7f); This code won't make it either. So I suspect it is not good idea

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi again, Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work. We cannot walk PCI bus because HT is not setup yet. Signed-off-by: Rudolf Marek r.ma...@assembler.cz

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Very good idea! It works! Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work. We cannot walk anything else than PCI bus 0 because HT is not setup yet. Signed-off-by:

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

Hi again, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,                                    PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); pci_write_config8(PCI_DEV(0,0x11,0), 0x41, 0x7f); This code won't make it either. So I suspect it is not good idea to walk whole PCI bus so early. Maybe HT

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

Very good idea! It works! Great. Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work. We cannot walk anything else than PCI bus 0 because HT is not setup yet. Signed-off-by: Rudolf Marek r.ma...@assembler.cz

[coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hello, Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work again (as it was in pre-tiny bootblock era) Signed-off-by: Rudolf Marek r.ma...@assembler.cz I had a strange

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

On 4/20/10 11:47 PM, Rudolf Marek wrote: Does it work better like this? /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) { /* Power management controller */ dev =

Re: [coreboot] [PATCH] Enable maximum decoded range for VT8237*

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 If not, we should make a test case and send it to eric. It does not. I tried what you suggested. What now? +static void bootblock_southbridge_init(void) { functions should have their opening bracket on the next line Aha ok will