On Thu, Oct 16, 2008 at 10:25 PM, Peter Stuge <[EMAIL PROTECTED]> wrote:
> Corey Osgood wrote:
> > Final fix for C7 boards, which are still using ROMCC, to be able to
> > build. As far as I know, no C7 boards currently in the tree use SPI
> > flash.
> >
> > Signed-off-by: Corey Osgood <[EMAIL PROT
Corey Osgood wrote:
> Final fix for C7 boards, which are still using ROMCC, to be able to
> build. As far as I know, no C7 boards currently in the tree use SPI
> flash.
>
> Signed-off-by: Corey Osgood <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
--
coreboot mailing list: coreboo
On Thu, Oct 16, 2008 at 10:10 PM, Corey Osgood <[EMAIL PROTECTED]>wrote:
> On Thu, Oct 16, 2008 at 9:28 PM, Eric W. Biederman <[EMAIL PROTECTED]>wrote:
>
>> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>>
>> > On 17.10.2008 02:50, Eric W. Biederman wrote:
>> >> Carl-Daniel Hailfinger <[EMAIL
On Thu, Oct 16, 2008 at 9:28 PM, Eric W. Biederman <[EMAIL PROTECTED]>wrote:
> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>
> > On 17.10.2008 02:50, Eric W. Biederman wrote:
> >> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> >>
> >>
> >>> I added a special case for ROMCC in the 0x..
Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> On 17.10.2008 02:50, Eric W. Biederman wrote:
>> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>>
>>
>>> I added a special case for ROMCC in the 0x...ULL constants in vt8237r.h.
>>> Please see r3664.
>>> The remaining segfault is being i
On 17.10.2008 02:50, Eric W. Biederman wrote:
> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>
>
>> I added a special case for ROMCC in the 0x...ULL constants in vt8237r.h.
>> Please see r3664.
>> The remaining segfault is being investigated by Eric.
>>
>
> It is reproducible, and it
Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> I added a special case for ROMCC in the 0x...ULL constants in vt8237r.h.
> Please see r3664.
> The remaining segfault is being investigated by Eric.
It is reproducible, and it happens as the intermediate expression is being
translated into inte
Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> On 17.10.2008 01:14, Eric W. Biederman wrote:
>> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>>
>>
>>> Hi Eric,
>>>
>>> I'm copying you on this mail because we managed to have ROMCC segfault
>>> reliably and choke on another piece of c
On 17.10.2008 02:17, Corey Osgood wrote:
> On Thu, Oct 16, 2008 at 7:32 PM, Carl-Daniel Hailfinger <
> [EMAIL PROTECTED]> wrote:
>
>
>> On 17.10.2008 01:14, Eric W. Biederman wrote:
>>
>>> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>>>
>>>
>>>
Hi Eric,
I'm copy
On 17.10.2008 01:32, Carl-Daniel Hailfinger wrote:
> On 17.10.2008 01:14, Eric W. Biederman wrote:
>
>> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>>
>>
>>
>>> Hi Eric,
>>>
>>> I'm copying you on this mail because we managed to have ROMCC segfault
>>> reliably and choke on anothe
On Thu, Oct 16, 2008 at 7:32 PM, Carl-Daniel Hailfinger <
[EMAIL PROTECTED]> wrote:
> On 17.10.2008 01:14, Eric W. Biederman wrote:
> > Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> >
> >
> >> Hi Eric,
> >>
> >> I'm copying you on this mail because we managed to have ROMCC segfault
> >> rel
On 17.10.2008 01:14, Eric W. Biederman wrote:
> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>
>
>> Hi Eric,
>>
>> I'm copying you on this mail because we managed to have ROMCC segfault
>> reliably and choke on another piece of code.
>>
>>
>> On 16.10.2008 18:36, Rudolf Marek wrote:
>>
Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> Hi Eric,
>
> I'm copying you on this mail because we managed to have ROMCC segfault
> reliably and choke on another piece of code.
>
>
> On 16.10.2008 18:36, Rudolf Marek wrote:
>>
>>> +#if 0
>>> /* Set SPI clock to 33MHz. */
>>> spire
Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> Hi Eric,
>
> I'm copying you on this mail because we managed to have ROMCC segfault
> reliably and choke on another piece of code.
Thanks.
> On 16.10.2008 18:36, Rudolf Marek wrote:
>>
>>> +#if 0
>>> /* Set SPI clock to 33MHz. */
>>>
On Thu, Oct 16, 2008 at 9:36 AM, Rudolf Marek <[EMAIL PROTECTED]> wrote:
> The reason why exactly this needs to be handled in rom stage is that the
> shadow registers needs to be filled _before_ PCI reset, because
> PCI reset will force the internal microcontroller to reload with this
> configurat
Hi Eric,
I'm copying you on this mail because we managed to have ROMCC segfault
reliably and choke on another piece of code.
On 16.10.2008 18:36, Rudolf Marek wrote:
>
>> +#if 0
>> /* Set SPI clock to 33MHz. */
>> spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
>> (*spireg) &= 0xf
Hello,
+#if 0
/* Set SPI clock to 33MHz. */
spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
(*spireg) &= 0xff00;
+#endif
This is OK because default is 16MHz, mtrr should handle caching for us.
+#if 0
if (rom == NULL) {
print_err("No config
Workaround v2 VIA ROMCC breakage.
Someone please tell me why the network adapter has to be handled by
romcc compiled code.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Index: LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r.h
=
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