Author: stepan
Date: Sun Dec 12 01:37:41 2010
New Revision: 6168
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6168
Log:
fix model 106cx
Signed-off-by: Stefan Reinauer <ste...@coreboot.org>
Acked-by: Stefan Reinauer <ste...@coreboot.org>
Modified:
trunk/src/cpu/intel/model_106cx/model_106cx_init.c
Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c
==============================================================================
--- trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sun Dec 12 00:28:17
2010 (r6167)
+++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sun Dec 12 01:37:41
2010 (r6168)
@@ -97,14 +97,16 @@
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
- // set P_BLK address
- msr = rdmsr(PMG_IO_BASE_ADDR);
- msr.lo = (PMB0 + 4) | (PMB1 << 16);
+ /* Set Processor MWAIT IO BASE (P_BLK) */
+ msr.hi = 0;
+ // TODO Do we want PM1_BASE? Needs SMM?
+ //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) <<
16);
+ msr.lo = ((PMB0_BASE + 4) & 0xffff);
wrmsr(PMG_IO_BASE_ADDR, msr);
- // set C_LVL controls
- msr = rdmsr(PMG_IO_CAPTURE_ADDR);
- msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because
LVL0+1 aren't counted
+ /* set C_LVL controls */
+ msr.hi = 0;
+ msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because
LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
}
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