Author: oxygene Date: Sat Dec 18 12:55:06 2010 New Revision: 6199 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6199
Log: A couple of Poulsbo fixes: - Don't include cmc.bin to the build. It's required, but we don't ship it - mptable's API changes a bit. Adapt. - Fix ACPI for new iasl versions with improved code validation Signed-off-by: Patrick Georgi <patrick.geo...@coresystems.de> Acked-by: Patrick Georgi <patrick.geo...@coresystems.de> Modified: trunk/src/mainboard/iwave/iWRainbowG6/mptable.c trunk/src/northbridge/intel/sch/acpi/hostbridge.asl trunk/src/southbridge/intel/sch/Makefile.inc Modified: trunk/src/mainboard/iwave/iWRainbowG6/mptable.c ============================================================================== --- trunk/src/mainboard/iwave/iWRainbowG6/mptable.c Sat Dec 18 08:48:43 2010 (r6198) +++ trunk/src/mainboard/iwave/iWRainbowG6/mptable.c Sat Dec 18 12:55:06 2010 (r6199) @@ -29,7 +29,7 @@ int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, "IWRAINBOWG6", LAPIC_ADDR); + mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); Modified: trunk/src/northbridge/intel/sch/acpi/hostbridge.asl ============================================================================== --- trunk/src/northbridge/intel/sch/acpi/hostbridge.asl Sat Dec 18 08:48:43 2010 (r6198) +++ trunk/src/northbridge/intel/sch/acpi/hostbridge.asl Sat Dec 18 12:55:06 2010 (r6199) @@ -23,6 +23,9 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI +Name(_ADR, 0) +Name(_BBN, 0) + Device (MCHC) { Name(_ADR, 0x00000000) // 0:0.0 @@ -204,17 +207,17 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00000000,,, TPMR) + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) }) // Find PCI resource area in MCRS Modified: trunk/src/southbridge/intel/sch/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/sch/Makefile.inc Sat Dec 18 08:48:43 2010 (r6198) +++ trunk/src/southbridge/intel/sch/Makefile.inc Sat Dec 18 12:55:06 2010 (r6199) @@ -35,7 +35,8 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c -cbfs-files-y += cmc.bin -cmc.bin-name := cmc.bin -cmc.bin-type := 0xaa -cmc.bin-position := 0xfffd0000 +# We don't ship that, but booting without it is bound to fail +#cbfs-files-y += cmc.bin +#cmc.bin-name := cmc.bin +#cmc.bin-type := 0xaa +#cmc.bin-position := 0xfffd0000 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot