[coreboot] Could not find a bounce buffer tested in minnowmax

2014-10-25 Thread DM365
I'm trying to investigate Coreboot and intel FSP in minnowmax board ,followed by "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372".‍‍ But ,the uart log show :Payload being loaded below 1MiB without region being marked as RAM usable.

Re: [coreboot] Could not find a bounce buffer tested in minnowmax

2014-09-17 Thread Mohan
On 09/17/14 21:26, Aaron Durbin wrote: On Wed, Sep 17, 2014 at 4:29 AM, DM365 <1395158...@qq.com> wrote: I'm trying to investigate Coreboot and intel FSP in minnowmax board ,followed by "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372".‍‍

Re: [coreboot] Could not find a bounce buffer tested in minnowmax

2014-09-17 Thread Aaron Durbin
On Wed, Sep 17, 2014 at 10:05 AM, ron minnich wrote: > So, in other words, this is one of those chipsets that is impossible > to make free of blobs, even if we do a full non-FSP coreboot port? That's orthogonal to this discussion, but I wouldn't dream of running baytrail w/o all these firmwares.

Re: [coreboot] Could not find a bounce buffer tested in minnowmax

2014-09-17 Thread ron minnich
So, in other words, this is one of those chipsets that is impossible to make free of blobs, even if we do a full non-FSP coreboot port? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Could not find a bounce buffer tested in minnowmax

2014-09-17 Thread Aaron Durbin
On Wed, Sep 17, 2014 at 4:29 AM, DM365 <1395158...@qq.com> wrote: > I'm trying to investigate Coreboot and intel FSP in minnowmax board > ,followed by > "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372".‍‍ > > But ,the uart log show : > >

[coreboot] Could not find a bounce buffer tested in minnowmax

2014-09-17 Thread DM365
I'm trying to investigate Coreboot and intel FSP in minnowmax board ,followed by "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372".‍‍ But ,the uart log show :Payload being loaded below 1MiB without region being marked as RAM usable.