[coreboot] Fwd: Denverton: NVMe not detected when serial console logs are disabled

[Sumo]

Hi Paul,

When logs are (almost) disabled the error isn't shown, so if I add the
delay with logs disabled the log output will have almost no difference at
all.

Following are the logs, including a log with Coreboot debug enabled + no
delay. For all logs FSP loglevel is set to NoDebug:
- nvme-err.log : no delay; coreboot debug_level=Error; NVMe error: at the
end of the log is shown the error in the UEFI FW:
  ERROR: C40000002:V02010007 I0 93B80004-9FB3-11D4-9A3A-0090273FC14D
7E90A998;
- nvme-ok-delay.log : 20ms delay; coreboot debug_level=Error; NVMe ok;
- nvme-ok.log : no delay; coreboot debug_level=Spew; NVMe ok: the coreboot
log output is enough to make NVMe work properly;

The NVMe is in the root port 00:0b.0, it is shown as 04:00.0

Thanks,
Sumo

On Mon, Aug 16, 2021 at 2:57 PM Paul Menzel <pmen...@molgen.mpg.de> wrote:

> Dear Sumo,
>
>
> Am 16.08.21 um 18:38 schrieb Sumo:
>
> > The NVMe is not detected when serial console logs are disabled, I mean by
> > setting both Coreboot log_level=Error (or less) and FSP
> > PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then
> > further on the device is not listed in the UEFI FW (same issue shown in
> > either CorebootPayloadPkg or UefiPayloadPkg). When Linux boots the device
> > appears normally.
> >
> > The problem is fixed by adding a small delay inside dev_enumerate() - a
> > 20ms delay at the very beginning of the function is enough. I'm wondering
> > if there is a better solution for this, the device is already defined in
> > the devicetree.cb (set as on). Maybe coreboot is too fast and the NVMe is
> > still booting up - or the PCIe link is still training, not sure. Coreboot
> > doesn't retry if the device is not detected right away?
>
> Please share the logs without and with the delay.
>
>
> Kind regards,
>
> Paul
>

nvme-ok.log
Description: Binary data

nvme-err.log
Description: Binary data

nvme-ok-delay.log
Description: Binary data

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