[coreboot] GPIO PADRSTCFG conflict in datasheet

Hi, I'm working on a skylake port and I've noticed something with the PADRSTCFG field of the GPIO Pad configuration. If you look at the 100-series datasheet volume 2 ( https://www-ssl.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html). The Pad configuration DW0 for GPP_A

Re: [coreboot] GPIO PADRSTCFG conflict in datasheet

Hi, I just found this file here : https://github.com/IntelFsp/FSP/blob/Skylake/SkylakeFspBinPkg/Include/GpioConfig.h It defines the reset values for GPIO in this enum : typedef enum { GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified GpioResetPwrGood = 0x1, ///< GPP: RSMRST; GPD: DS