No hint, anyone?
On Wed, Dec 02, 2009 at 03:44:15PM +0100, Daniel Mack wrote:
On Wed, Dec 02, 2009 at 02:59:01PM +0100, Peter Stuge wrote:
Daniel Mack wrote:
the effect is harder to trigger when booting from an external LPC
flash emulator (in contrast to coreboot flashed to the internal
On Fri, Dec 4, 2009 at 9:47 AM, Daniel Mack dan...@caiaq.de wrote:
No hint, anyone?
Maybe you could zero all the RAM. If you have to power it down for a
specific amount of time, that could be the time for the RAM to lose
its state. If that works, you could start finding uninitialized
variables
On Fri, Dec 4, 2009 at 8:47 AM, Daniel Mack dan...@caiaq.de wrote:
No hint, anyone?
Just about every time I had this problem on my geodes it was a problem
with dram. Just about every time. It's quite weird how well DRAM can
work even if it has not been programmed correctly. The correspondance
Hi Ron,
thanks for your answer.
On Fri, Dec 04, 2009 at 09:03:14AM -0800, ron minnich wrote:
On Fri, Dec 4, 2009 at 8:47 AM, Daniel Mack dan...@caiaq.de wrote:
No hint, anyone?
Just about every time I had this problem on my geodes it was a problem
with dram. Just about every time. It's
(sorry I can't post a proper reply message, I picked that up from the
archives)
Nathan Williams nathan at traverse.com.au wrote:
I am suspicious that the reset problem only occurs when I'm using a
laptop hard drive off the 44pin IDE connector on our board. I have tried
booting with a 3.5
Daniel Mack wrote:
the effect is harder to trigger when booting from an external LPC
flash emulator (in contrast to coreboot flashed to the internal
LPC).
Then you could experiment with a few different flash chips.
PC Engines makes a nice and neat Flash recovery board, which plugs
onto the
On Wed, Dec 02, 2009 at 02:59:01PM +0100, Peter Stuge wrote:
Daniel Mack wrote:
the effect is harder to trigger when booting from an external LPC
flash emulator (in contrast to coreboot flashed to the internal
LPC).
Then you could experiment with a few different flash chips.
PC
On Fri, Nov 27, 2009 at 2:05 AM, Nathan Williams nat...@traverse.com.au wrote:
Nathan Williams wrote:
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au
Marc Jones wrote:
On Fri, Nov 27, 2009 at 2:05 AM, Nathan Williams nat...@traverse.com.au
wrote:
Nathan Williams wrote:
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
Nathan Williams wrote:
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it
Marc Jones wrote:
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it
with coreboot:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it with
coreboot:
http://coreboot.pastebin.com/m39b22c21
The only differences I can see are related to interrupts, which
On Tue, Nov 24, 2009 at 1:09 AM, Nathan Williams nat...@traverse.com.au wrote:
Marc Jones wrote:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
I managed to get the commercial BIOS to boot on my board and diffed it with
coreboot:
On Mon, Nov 23, 2009 at 12:27 AM, Nathan Williams
nat...@traverse.com.au wrote:
Marc Jones wrote:
On Tue, Nov 10, 2009 at 1:26 PM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au
wrote:
Another
Marc Jones wrote:
On Tue, Nov 10, 2009 at 1:26 PM, Nathan Williams nat...@traverse.com.au
wrote:
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au
wrote:
Another observation I made was that by setting the debug_level to
BIOS_CRIT,
instead of dying at
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au wrote:
Another observation I made was that by setting the debug_level to BIOS_CRIT,
instead of dying at the usual spot in disable_car() and stopping, coreboot
would reset continuously (cycling every 1-2
On Tue, Nov 10, 2009 at 1:26 PM, Nathan Williams nat...@traverse.com.au wrote:
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au
wrote:
Another observation I made was that by setting the debug_level to
BIOS_CRIT,
instead of dying at the usual spot in
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au wrote:
Marc Jones wrote:
When linux does the reset, is the coreboot output the same? Does it do
the Resetting the processor?
Yes, it does Resetting the processor after PLL configuration for the
changes to take effect
I
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