Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Igor Skochinsky via coreboot
Hello Konrad, Sunday, January 21, 2018, 9:29:35 PM, you wrote: KE> Hi Igor, I know your work and I want to give kudos to you. However without being  KE> kritical (it is just like that) I want to note the tips you read i.e. at  winraid.com KE> really make you just more confused - eather they are

Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Konrad Eisele
> > > XMLs are stored in compressed format (as Qt resource) inside the FIT > binary. You can find one approach of extracting them in Positive > Technologies blog: > > http://blog.ptsecurity.com/2017/04/intel-me-way-of-static-analysis.html > > You can indeed use FIT for setting the strap but you'll

Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Igor Skochinsky via coreboot
Hello Konrad, Sunday, January 21, 2018, 3:12:07 PM, you wrote: KE> You can probably set the DCI enable bit in the PCH softstraps in the KE> descriptor, no need to mess with the BIOS editing.  It seems to be bit 17 KE> in strap 0, right next to the HAP bit: KE> value="0x1" offset="0x0"  bitfield

Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Konrad Eisele
> > You can probably set the DCI enable bit in the PCH softstraps in the > descriptor, no need to mess with the BIOS editing. It seems to be bit 17 > in strap 0, right next to the HAP bit: > > offset="0x0" bitfield_high="17" bitfield_low="17" /> > offset="0x0" bitfield_high="16" bitfield_low="

Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Igor Skochinsky via coreboot
Hello Konrad, Sunday, January 21, 2018, 9:02:30 AM, you wrote: KE> I would like to control the DCI and Debug bits in the boot process KE> and  dont want to mess with the AMI bios patching. You can probably set the DCI enable bit in the PCH softstraps in the descriptor, no need to mess with the B

Re: [coreboot] Gigabyte Brix

2018-01-21 Thread Konrad Eisele
I would like to control the DCI and Debug bits in the boot process and dont want to mess with the AMI bios patching. I was wondering weather there is a port that is near enough so that it might boot at lease long enough so that I can hook up with the DCI cable... 2018-01-20 23:56 GMT+00:00 taii...

Re: [coreboot] Gigabyte Brix

2018-01-20 Thread taii...@gmx.com
On 01/20/2018 06:38 PM, Konrad Eisele wrote: Is there a chance to get coreboot running on a GB-BKi5HA-7200 (i5-7200 Kabylake) or a GB-BSi3-6100 (i3-6100 Skylake)? You would have to do a port, which requires you have extensive programming skills or a large amount of money to pay someone to do it

[coreboot] Gigabyte Brix

2018-01-20 Thread Konrad Eisele
Is there a chance to get coreboot running on a GB-BKi5HA-7200 (i5-7200 Kabylake) or a GB-BSi3-6100 (i3-6100 Skylake)? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot