[coreboot] IMB-A180 based design question regarding POST codes during boot failure

2014-06-19 Thread Mark C. Mason
We have a board that is failing to boot, and we think there is a memory problem on the board. I have a trace (od -t x4 dump) of the POST codes: 000 01 10 10 a0 a1 a1 30 31 34 37 c0 b1 c1 38 39 c4 020 71 72 75 76 77 78 79 7b 7a 7c 90 91 91 58 5a 01 040 10 10 a0 a1 a1 34 37 c0 c1 38 3

Re: [coreboot] IMB-A180 based design question regarding POST codes during boot failure

2014-06-19 Thread Dave Frodin
Mark, Can you describe your memory SODIMM config? Are you loading both SODIMMs? An engineer here suggests you set BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE in the mainboard buildOpts.c file. Thanks, Dave On Thu, Jun 19, 2014 at 12:37 PM, Mark C. Mason wrote: > > We have a board that is failing to bo

Re: [coreboot] IMB-A180 based design question regarding POST codes during boot failure

2014-06-19 Thread Peter Stuge
Dave, Dave Frodin wrote: > An engineer here suggests you set BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE > in the mainboard buildOpts.c file. Can you please provide more information. I think it is incredibly embarrassing that coreboot has code which requires manually messing with #defines depending on some

Re: [coreboot] IMB-A180 based design question regarding POST codes during boot failure

2014-06-19 Thread Dave Frodin
Peter, It was intended as a debug step. That engineer is working through similar issues on a similar chipset that has problems with multiple DIMMs and suggested it be tried. Dave On Thu, Jun 19, 2014 at 1:33 PM, Peter Stuge wrote: > Dave, > > Dave Frodin wrote: > > An engineer here suggests y

Re: [coreboot] IMB-A180 based design question regarding POST codes during boot failure

2014-06-20 Thread Mark C. Mason
Dave, I was ready to boot your suggestion and the hardware guys said: "We know there's no clock", then soon after had it booting normally. Good call.  This was indeed a debugging session, not a coreboot issue. A bit of history.  Our design